Patents by Inventor Chien-Fu Huang
Chien-Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118721Abstract: A regulator circuit module, a memory storage device, and a voltage control method are disclosed. The voltage control method includes: generating an output voltage according to an input voltage by a driving circuit; generating a feedback voltage according to the output voltage; and controlling the driving circuit by a first regulator circuit to adjust the output voltage in response to a current change caused by the feedback voltage.Type: ApplicationFiled: November 23, 2022Publication date: April 11, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Huang, Bing-Wei Yi
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Patent number: 11944017Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.Type: GrantFiled: May 5, 2023Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20240099150Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 11901480Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.Type: GrantFiled: August 9, 2021Date of Patent: February 13, 2024Assignee: EPISTAR CORPORATIONInventors: Chien-Fu Huang, Chih-Chiang Lu, Chun-Yu Lin, Hsin-Chih Chiu
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Patent number: 11887529Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.Type: GrantFiled: April 19, 2022Date of Patent: January 30, 2024Assignee: Au Optronics CorporationInventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
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Publication number: 20230234033Abstract: A composite solid base catalyst, a manufacturing method thereof and a manufacturing method of glycidol are provided. The composite solid base catalyst includes an aluminum carrier and a plurality of calcium particles. The plurality of calcium particles are supported by the aluminum carrier. Beta basic sites of the composite solid base catalyst are 0.58 mmol/g-3.89 mmol/g.Type: ApplicationFiled: June 14, 2022Publication date: July 27, 2023Inventors: De-Hao TSAI, Yung-Tin PAN, Che-Ming YANG, Ching-Yuan CHANG, Ding-Huei TSAI, Chien-Fu HUANG, Yi-Ta TSAI
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Patent number: 11710763Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.Type: GrantFiled: September 10, 2021Date of Patent: July 25, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung-Kuang Chen, Chia-Ching Li, Chien-Fu Huang, Chia-Ming Hu
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Publication number: 20230187473Abstract: A light-emitting device includes a substrate with a top surface; a first light-emitting structure unit and a second light-emitting structure unit separately formed on the top surface and adjacent to each other, and wherein the first light-emitting structure unit includes a first sidewall and the second light-emitting structure unit includes a second sidewall; an isolation layer formed on the first sidewall and the second sidewall, including a first edge on the first light-emitting structure unit and wherein the first edge has an acute angle in a cross-sectional view; and an electrical connection formed on the isolation layer, the first light-emitting structure unit and the second light-emitting structure unit, and electrically connecting the first light-emitting structure unit and the second light-emitting structure unit; wherein the first sidewall and the second sidewall are inclined; and wherein the electrical connection includes a first part on the first light-emitting structure unit, and the first part doType: ApplicationFiled: February 2, 2023Publication date: June 15, 2023Inventors: Chien-Fu SHEN, Chao-Hsing CHEN, Tsun-Kai KO, Schang-Jing HON, Sheng-Jie HSU, De-Shan KUO, Hsin-Ying WANG, Chiu-Lin YAO, Chien-Fu HUANG, Hsin-Mao LIU, Chien-Kai CHUNG
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Patent number: 11594573Abstract: A light-emitting device, includes a substrate with a top surface; a first light-emitting structure unit and a second light-emitting structure unit separately formed on the top surface and adjacent to each other, and wherein the first light-emitting structure unit includes a first sidewall and a second sidewall; a trench between the first and the second light-emitting structure units; and an electrical connection arranged on the first sidewall and the second light-emitting structure unit, and electrically connecting the first light-emitting structure unit and the second light-emitting structure unit; wherein the first sidewall connects to the top surface; wherein the first sidewall faces the second light-emitting structure units, and the second sidewall is not between the first light-emitting structure unit and the second light-emitting structure unit; and wherein the second sidewall is steeper than the first sidewall.Type: GrantFiled: February 8, 2021Date of Patent: February 28, 2023Assignee: EPISTAR CORPORATIONInventors: Chien-Fu Shen, Chao-Hsing Chen, Tsun-Kai Ko, Schang-Jing Hon, Sheng-Jie Hsu, De-Shan Kuo, Hsin-Ying Wang, Chiu-Lin Yao, Chien-Fu Huang, Hsin-Mao Liu, Chien-Kai Chung
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Patent number: 11514852Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.Type: GrantFiled: April 20, 2022Date of Patent: November 29, 2022Assignee: Au Optronics CorporationInventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
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Publication number: 20220335887Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.Type: ApplicationFiled: April 20, 2022Publication date: October 20, 2022Applicant: Au Optronics CorporationInventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
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Publication number: 20220335886Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.Type: ApplicationFiled: April 19, 2022Publication date: October 20, 2022Applicant: Au Optronics CorporationInventors: Ya-Jung Wang, Jing-Wun Jhang, Rong-Fu Lin, Nien-Chen Li, Hsien-Chun Wang, Che-Chia Chang, June Woo Lee, Hsin-Ying Lin, Chia-Ting Hsieh, Chien-Fu Huang, Sung-Yu Su
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Publication number: 20220336523Abstract: The present disclosure provides a semiconductor device, including a buffer layer, a first sub-chip and a second sub-chip, and a connecting element. The first sub-chip and the second sub-chip are separately arranged on the buffer layer. Each of the first sub-chip and the second sub-chip includes a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially arranged on the buffer layer in a top-down approach. The first diffusion layer and the buffer layer are first-type epitaxial layers, and the second diffusion layer is a second-type epitaxial layer. The connecting element is configured to couple the second diffusion layer of the first sub-chip and the first diffusion layer of the second sub-chip.Type: ApplicationFiled: April 15, 2022Publication date: October 20, 2022Inventors: Chia-Ting HSIEH, Chien-Fu HUANG, Cheng-Nan YEH, Seok-Lyul LEE, Yung-Hsiang LAN, June-Woo LEE, Sung-Yu SU, Hsien-Chun WANG, Ya-Jung WANG, Hsin-Ying LIN, Yu-Chieh LIN, Yang-En WU
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Publication number: 20220336425Abstract: The present disclosure provides a light emitting diode component, including a body and a plurality of P-N diode structures. The P-N diode structures are coupled in series and integrated on the body. The P-N diode structures include a plurality of p-type doping layers and a plurality of n-type doping layers. The p-type doping layer of a first P-N diode structure in the P-N diode structures is electrically coupled to the n-type doping layer of a second P-N diode structure in the P-N diode structures.Type: ApplicationFiled: April 19, 2022Publication date: October 20, 2022Inventors: June-Woo LEE, Yang-En WU, Sung-Yu SU, Hsien-Chun WANG, Ya-Jung WANG, Chia-Ting HSIEH, Chien-Fu HUANG, Hsin-Ying LIN
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Patent number: 11282581Abstract: A memory device has a plurality of blocks of memory cells and a plurality of bit lines, each block including a group of word lines, and a set of NAND strings. Each block in the plurality of blocks of memory cells has a plurality of sub-blocks, each sub-block including a distinct subset of the set of NAND strings of the block selected, and a respective sub-block string select line. Control circuits are configured to execute a program operation including applying word line voltages and string select line voltages at a precharge level to precharge the set of NAND strings in the selected block, then lowering the gate voltages on all the sub-block string select lines of the block, and then lowering the word line voltages on the group of word lines. Thereafter, the program of cells in a selected sub-block is executed.Type: GrantFiled: January 4, 2021Date of Patent: March 22, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Han-Sung Chen, Chien-Fu Huang
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Publication number: 20210408226Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Inventors: Chung-Kuang CHEN, Chia-Ching LI, Chien-Fu HUANG, Chia-Ming HU
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Publication number: 20210367098Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Chien-Fu HUANG, Chih-Chiang LU, Chun-Yu LIN, Hsin-Chih CHIU
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Publication number: 20210325261Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.Type: ApplicationFiled: September 3, 2020Publication date: October 21, 2021Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chia-Ming HU, Chung-Kuang CHEN, Chia-Ching LI, Chien-Fu HUANG
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Patent number: 11152458Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.Type: GrantFiled: February 7, 2020Date of Patent: October 19, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung-Kuang Chen, Chia-Ching Li, Chien-Fu Huang, Chia-Ming Hu
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Publication number: 20210249504Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.Type: ApplicationFiled: February 7, 2020Publication date: August 12, 2021Inventors: Chung-Kuang CHEN, Chia-Ching LI, Chien-Fu HUANG, Chia-Ming HU