Abstract: A power path switch circuit includes: a power transistor unit including: a first vertical double-diffused metal oxide semiconductor (VDMOS) device, wherein a first current outflow end of the first VDMOS device is coupled to an output end of a power path; and a second VDMOS device, wherein a first current inflow end of the first VDMOS device and a second current inflow end of the second VDMOS device are coupled with a supply end of the power path; and a voltage locking circuit coupled to the first current outflow end and the second current outflow end, for locking a voltage at the second current outflow end to a voltage at the first current outflow end, so that there is a predetermined ratio between a first conductive current flowing through the first VDMOS device and a second conductive current flowing through the second VDMOS device.

Abstract: A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.

Abstract: A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.

Abstract: A low delay time power converter circuit includes a driver circuit and a load. The driver circuit generates a switching driving signal to control the load. The driver circuit includes a switching control circuit and an output stage circuit which includes a first power switch, a second power switch and an impedance adjusting circuit. When the switching control circuit controls the switching driving signal to a first voltage level at a first time point, the first power switch is turned ON and then is turned OFF after a predetermined period. When the switching control circuit controls the switching driving signal to a second voltage level at a second time point, the second power switch is turned ON. The time point when the first power switch is turned OFF is earlier than the second time point. A resistance of the impedance adjusting circuit is larger than a conductive resistance of the first power switch.

Abstract: A power path switch circuit includes: a power transistor unit including: a first vertical double-diffused metal oxide semiconductor (VDMOS) device, wherein a first current outflow end of the first VDMOS device is coupled to an output end of a power path; and a second VDMOS device, wherein a first current inflow end of the first VDMOS device and a second current inflow end of the second VDMOS device are coupled with a supply end of the power path; and a voltage locking circuit coupled to the first current outflow end and the second current outflow end, for locking a voltage at the second current outflow end to a voltage at the first current outflow end, so that there is a predetermined ratio between a first conductive current flowing through the first VDMOS device and a second conductive current flowing through the second VDMOS device.

Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.

Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.

Abstract: A low delay time power converter circuit includes a driver circuit and a load. The driver circuit generates a switching driving signal to control the load. The driver circuit includes a switching control circuit and an output stage circuit which includes a first power switch, a second power switch and an impedance adjusting circuit. When the switching control circuit controls the switching driving signal to a first voltage level at a first time point, the first power switch is turned ON and then is turned OFF after a predetermined period. When the switching control circuit controls the switching driving signal to a second voltage level at a second time point, the second power switch is turned ON. The time point when the first power switch is turned OFF is earlier than the second time point. A resistance of the impedance adjusting circuit is larger than a conductive resistance of the first power switch.

Abstract: Whether a synchronous signal includes a synchronous pulse is determined by detecting whether there is a positive pulse higher than a positive threshold followed by a negative pulse lower than a negative threshold. The pulse signal detection method includes: comparing the synchronous signal with the positive threshold; comparing the synchronous signal with the negative threshold; and determining that the synchronous pulse exists when the positive pulse of the synchronous signal is higher than the positive threshold and the negative pulse of the synchronous signal is lower than the negative threshold in a post detection period after the positive pulse of the synchronous signal is determined higher than the positive threshold.

Abstract: Whether a synchronous signal includes a synchronous pulse is determined by detecting whether there is a positive pulse higher than a positive threshold followed by a negative pulse lower than a negative threshold. The pulse signal detection method includes: comparing the synchronous signal with the positive threshold; comparing the synchronous signal with the negative threshold; and determining that the synchronous pulse exists when the positive pulse of the synchronous signal is higher than the positive threshold and the negative pulse of the synchronous signal is lower than the negative threshold in a post detection period after the positive pulse of the synchronous signal is determined higher than the positive threshold.

Abstract: A ZVS (zero voltage switching) control circuit for use in a flyback power converter includes a primary side controller and a secondary side controller. The primary side controller generates a switching signal to control a power transformer through a power transistor to generate an output voltage. The secondary side controller generates an SR (synchronous rectifier) signal to control an SR transistor at a secondary side of the power transformer. The SR signal includes an SR-control pulse and a ZVS pulse. The SR-control pulse controls the SR transistor according to a demagnetizing period of the power transformer. The ZVS pulse determines the starting timing of the switching signal to achieve zero voltage switching for the power transistor. The secondary side controller generates the ZVS pulse after a delay time from when the power transformer is demagnetized. The delay time is determined according to an output load of the output voltage.

Abstract: A ZVS (zero voltage switching) control circuit for use in a flyback power converter includes a primary side controller and a secondary side controller. The primary side controller generates a switching signal to control a power transformer through a power transistor to generate an output voltage. The secondary side controller generates an SR (synchronous rectifier) signal to control an SR transistor at a secondary side of the power transformer. The SR signal includes an SR-control pulse and a ZVS pulse. The SR-control pulse controls the SR transistor according to a demagnetizing period of the power transformer. The ZVS pulse determines the starting timing of the switching signal to achieve zero voltage switching for the power transistor. The secondary side controller generates the ZVS pulse after a delay time from when the power transformer is demagnetized. The delay time is determined according to an output load of the output voltage.

Abstract: A discrete-time current sense circuit includes: a current mirror circuit, which includes: a power switch, for providing the communication current; and a sampling switch, which is for sampling the communication protocol current in a sampling period in a discrete manner, to generate a sampling current; a bias circuit, for providing a reference voltage to the reference node in the sampling period according to a communication protocol voltage of the communication protocol voltage node; a signal conversion circuit, for generating the discrete-time current sense signal according to the sampling current; and a first switch, for operating to determine the sampling period; wherein the sampling period is part of a complete period in which the power switch provides the communication protocol current.

Abstract: A flyback power converter includes: a transformer, a power switch, a switch control unit, a synchronous rectifier switch and a secondary side control circuit. The secondary side control circuit includes: a switch signal generation circuit and a first power conversion circuit. The secondary side control circuit is coupled to the synchronous rectifier switch and the secondary winding of the transformer. The switch signal generation circuit generates the synchronous rectifier switch signal selectively according to a first power or a second power, to control the synchronous rectifier switch. The first power is related to the output voltage. The first power conversion circuit generates the second power according to a secondary phase signal on a phase node between the secondary winding of the transformer and the synchronous rectifier switch.

Abstract: The present invention provides a power switch control circuit and an open detection method thereof. The power switch control circuit is for generating an operation signal at an operation signal output pin according to an input signal, wherein the operation signal is for operating a power switch. The power switch control circuit includes: a current injection circuit, which is connected to the operation signal output pin, and provides a predetermined current to the operation signal output pin according to an enable signal; and an open detection circuit, which is coupled to the current injection circuit, and determines whether a connection between the operation signal output pin and the power switch is open according to a level of the operation signal output pin at a detection time point or according to a level variation of the operation signal output pin during a detection time period, whereby an open detection signal is generated.

Abstract: A discrete-time current sense circuit includes: a current mirror circuit, which includes: a power switch, for providing the communication current; and a sampling switch, which is for sampling the communication protocol current in a sampling period in a discrete manner, to generate a sampling current; a bias circuit, for providing a reference voltage to the reference node in the sampling period according to a communication protocol voltage of the communication protocol voltage node; a signal conversion circuit, for generating the discrete-time current sense signal according to the sampling current; and a first switch, for operating to determine the sampling period; wherein the sampling period is part of a complete period in which the power switch provides the communication protocol current.

Abstract: A flyback power converter circuit converting an input voltage to an output voltage includes a transformer, a power switch, a synchronous rectifier (SR) switch, and a secondary side control circuit. The secondary side control circuit controls the SR switch to be ON when the power switch is OFF. The secondary side control circuit includes a driving switch for controlling the SR switch, a synchronous control circuit powered by a voltage related to the output voltage, which controls the driving switch to operate the SR switch, and a clamping circuit including a clamping switch and a clamping switch control circuit. The clamping switch control circuit controls the clamping switch according to a current inflow terminal voltage of the clamping switch and/or the voltage related to the output voltage, such that, during a secondary side power-on period, an equivalent impedance of the current inflow terminal of the clamping switch is smaller than a predetermined clamping impedance.

Abstract: A switching regulator includes: a controller power ON reset (POR) circuit, a controller post-POR signal generation circuit, and a pulse width modulation (PWM) signal generation circuit. The controller post-POR signal generation circuit switches the controller post-POR signal to a ready level after a controller pre-POR signal is switched to a controller reset-accomplished level and a driver signal starts switching levels to operate a power switch. The PWM signal generation circuit sets a duty ratio of a PWM signal to a predetermined minimum duty ratio after the controller pre-POR signal is switched to the controller reset-accomplished level and before the controller post-POR signal is switched to a ready level.

Abstract: A flyback power converter includes a transformer having an auxiliary winding for generating an auxiliary voltage and providing a supply voltage on a supply node; a primary side controller circuit which is powered by the supply voltage from the supply node; and a high voltage (HV) start-up circuit. The HV start-up circuit is coupled to an high voltage signal through a HV input terminal and generates the supply voltage through a supply output terminal, wherein when the supply voltage does not exceed a start-up voltage threshold, a HV start-up switch conducts the HV input terminal and the supply output terminal to provide the supply voltage, and when the supply voltage exceeds a start-up voltage threshold, the HV start-up switch is OFF. The HV start-up circuit and the primary side controller circuit are packaged in two separate integrated circuit packages respectively.

Abstract: A switching regulator includes: a controller power ON reset (POR) circuit, a controller post-POR signal generation circuit, and a pulse width modulation (PWM) signal generation circuit. The controller post-POR signal generation circuit switches the controller post-POR signal to a ready level after a controller pre-POR signal is switched to a controller reset-accomplished level and a driver signal starts switching levels to operate a power switch. The PWM signal generation circuit sets a duty ratio of a PWM signal to a predetermined minimum duty ratio after the controller pre-POR signal is switched to the controller reset-accomplished level and before the controller post-POR signal is switched to a ready level.