Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.

Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: A pixel structure includes a first patterned transparent conductive layer, an active layer, an insulating layer and a second patterned transparent conductive layer. The first patterned transparent conductive layer is disposed on a substrate and includes a source, a drain and a pixel electrode connected to the drain. The active layer connects the source and the drain. The insulating layer covers the source, the drain and the active layer. The second patterned transparent conductive layer is disposed on the insulating layer and includes a gate disposed above the active layer and a common electrode disposed above the pixel electrode. A fabrication method of a pixel structure is also provided.

Abstract: A pixel structure and a manufacturing method of the pixel structure are provided. The pixel structure includes a substrate, a transistor, a planarizing layer, a plurality of contact windows, and a pixel electrode layer. The transistor is disposed on the substrate and includes a gate, a source, and a drain. The planarizing layer is disposed on the gate, the source, and a portion of the drain. The contact windows penetrate the planarizing layer and expose another portion of the drain. The pixel electrode layer is disposed on the planarizing layer, on the another portion of the drain, and in the contact windows and is electrically connected to the drain.

Abstract: A pixel structure includes a first patterned transparent conductive layer, an active layer, an insulating layer and a second patterned transparent conductive layer. The first patterned transparent conductive layer is disposed on a substrate and includes a source, a drain and a pixel electrode connected to the drain. The active layer connects the source and the drain. The insulating layer covers the source, the drain and the active layer. The second patterned transparent conductive layer is disposed on the insulating layer and includes a gate disposed above the active layer and a common electrode disposed above the pixel electrode. A fabrication method of a pixel structure is also provided.

Abstract: A pixel structure and a manufacturing method of the pixel structure are provided. The pixel structure includes a substrate, a transistor, a planarizing layer, a plurality of contact windows, and a pixel electrode layer. The transistor is disposed on the substrate and includes a gate, a source, and a drain. The planarizing layer is disposed on the gate, the source, and a portion of the drain. The contact windows penetrate the planarizing layer and expose another portion of the drain. The pixel electrode layer is disposed on the planarizing layer, on the another portion of the drain, and in the contact windows and is electrically connected to the drain.