Abstract: A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.

Abstract: A wireless device for selecting a connection target based on signal quality, a system and a method thereof are provided. The invention selects a candidate device having the best signal quality and duration of the signal quality is not less than a threshold reaching a certain time. If the selected candidate device also selects the wireless device, a unique connection is established between the wireless device and the candidate device. In a dynamical and complicated environment, the disclosed system and the method can build up a stable linear topology through automatic negotiation among wireless devices. The invention then achieves the effect of updating topology in time to adapt to environment changes.

Abstract: A wireless device for selecting a connection target based on signal quality, a system and a method thereof are provided. The invention selects a candidate device having the best signal quality and duration of the signal quality is not less than a threshold reaching a certain time. If the selected candidate device also selects the wireless device, a unique connection is established between the wireless device and the candidate device. In a dynamical and complicated environment, the disclosed system and the method can build up a stable linear topology through automatic negotiation among wireless devices. The invention then achieves the effect of updating topology in time to adapt to environment changes.