Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.

Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Abstract: The disclosure provides an eye state assessment method and an electronic device. The method includes: obtaining an optic disc image area from a first fundus photography and generating multiple optic cup-to-disc ratio assessment results by multiple first models based on the optic disc image area; obtaining a first assessment result of an eye based on the optic cup-to-disc ratio assessment results; performing multiple data augmentation operations on the first fundus photography to generate multiple second fundus photographies; generating multiple retinal nerve fiber layer (RNFL) defect assessment results by multiple second models based on the second fundus photographies; obtaining a second assessment result of the eye based on the RNFL defect assessment results; and obtaining an optic nerve assessment result of the eye based on the first assessment result and the second assessment result.

Abstract: A semiconductor device including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure and a second connector structure is provided. The first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, wherein the first connector structure has a third lateral dimension greater than the first lateral dimension. The second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension.

Abstract: A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.

Abstract: A method for etching a tungsten silicide (WSix) layer during formation of a gate electrode in an integrated circuit is disclosed. The method uses an etchant gas comprising nitrogen gas (N2) and oxygen gas (O2) in a specified flow ratio. The etchant gas may also comprise chlorine gas (Cl2) and tetrafluoromethane (CF4). The selectivity of the etchant gas containing O2 for WSix versus polysilicon is much higher, which reduces overetching and provides more control in methods for producing a gate electrode. A gate electrode produced by such a method is also disclosed.

Abstract: A fan module including a body and a plurality of blades is provided. The body has a rotating axis and the body is telescopic along the rotating axis to have an elongated state and a shortened state. The blades are respectively disposed on the body and rotate along with the body along the rotating axis. At least a portion of each blade is flexible and a bending state of each blade is changed along with the elongated state or the shortened state of the body. An axial size of each blade along the rotating axis when the body is in the elongated state is greater than the axial size of each blade along the rotating axis when the body is in the shortened state.

Abstract: The present invention relates to a method for size estimation by image recognition of a specific target using a given scale. First, a reference objected is recognized in an image and the corresponding scale is established. Then the specific target is searched and the size of the specific target is estimated according to the acquired scale.

Abstract: A connector in an information handling system includes a battery connector, a battery receptacle, and a signal pin structure contact. The battery connector includes a first set of power pins and a first set of signal pins. The battery receptacle includes a second set of power pins and a second set of signal pins. The first and second sets of power pins are coupled together when the battery connector is inserted within the battery receptacle. The signal pin structure contact transitions between an open position and a closed position. The signal pin structure contact couples the first and second sets of signal pins when the signal pin structure contact is in the closed position. A power down signal is provided to components of the information handling system when the signal pin structure contact is in the open position.

Abstract: This application describes covers for electronic devices, electronic devices, and methods for making the covers. In one example, described herein is a cover for an electronic device comprising: a substrate comprising a metal; a passivation layer or a micro-arc oxidation layer deposited on at least one surface of the substrate; a primer coating layer on the passivation layer or the micro-arc oxidation layer; an optional base coating layer on the primer coating layer; a top coating layer on the optional base coating layer or on the primer coating layer; and a hydrophobic coating layer.

Abstract: An information handling system is configured to implement a battery management method and perform battery management operations including receiving information indicative of an operating system associated with the information handling system and determining a battery behavior environment (BBE) based, at least in part, on the operating system. A battery management unit (BMU) profile associated with the battery behavior environment may be selected, wherein the BMU profile indicates settings for one or more battery management parameters. The BMU is then configured in accordance with the BMU profile and the battery is managed in accordance with the BMU profile.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first heat conductive layer between the heat-spreading wall structure and the chip. The chip package structure includes a second heat conductive layer over the chip and surrounded by the first heat conductive layer. The chip package structure includes a heat-spreading lid over the substrate and covering the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.

Abstract: In example implementations, an enclosure is provided. The enclosure includes a first layer of carbon fiber and a second layer of a carbon fiber pattern fabricated from a plastic. The first layer of carbon fiber is formed in a shape of a portable electronic device. An antenna window is formed in the first layer of the carbon fiber. The second layer of the carbon fiber pattern has a same shape and a same size as the first layer of carbon fiber.

Abstract: An optical module and a projection apparatus using the optical module are provided. The optical module includes a base, a first frame, an optical element and at least one driving assembly. The first frame is disposed in the base. The optical element is disposed in the first frame. The at least one driving assembly is disposed between the base and the first frame. The first frame is configured to move relative to the base by a magnetic force generated by the at least one driving assembly. Each of the at least one driving assembly includes a coil and a Halbach array magnet structure, the coil and the Halbach array magnet structure face each other along a first direction, a width of the Halbach array magnet structure in the first direction is W1, and a width of the coil in the first direction is W2, and 0.7?W1/W2?2.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.