Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A memory device is formed in an interconnect structure over a substrate. Forming the memory device includes forming an alternating stack of dielectric material layers and conductive material layers, wherein the alternating stack includes a memory array region and a staircase region adjacent to the memory array region; forming a trench on the memory array region of the alternating stack; forming a data storage layer, channel layers, bit line pillars, and source line pillars in the trench; and performing patterning processes to from a staircase structure on the staircase region. The staircase structure steps downward from a first direction and makes a 180-degree turn to step downward in a second direction opposite to the first direction.

Abstract: A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: An apparatus includes a plurality of CPUs, a CPU scheduler, an idle predictor, and a CPU-idle framework. The CPUs are categorized into a first group and a second group, and a specific CPU is in the first group. When the specific CPU is idle, the CPU scheduler executes an idle task. The idle predictor determines whether the CPUs in the first group corresponding to the specific CPU are going to operate the sleep mode in response to the idle task so as to schedule a sleep schedule of the CPUs in the first group operating in the sleep mode. The CPU-idle framework commands the CPUs in the first group to operate in the sleep mode based on the sleep schedule.

Abstract: A multi-processor system includes multiple processors arranged in multiple clusters. Different clusters have different power and performance characteristics. The system includes a task scheduler to schedule tasks to the processors. The task scheduler, in response to detection of a scheduling event trigger, is operative to identify a scheduling objective between a first objective of energy optimization and a second objective of load balance. The scheduling objective is identified based on at least respective operating frequencies and loading of all processors in a highest-capacity cluster of the multiple clusters. According to the identified scheduling objective, the task scheduler schedules a given task to a processor selected among the processors in the multiple clusters.

Abstract: Nucleic acid aptamers capable of binding to lymphocyte activation gene 3 (LAG-3) and uses thereof for modulating immune responses. Such aptamers may comprise a G-rich motif, for example, GX1GGGX2GGTX3A (SEQ ID No: 1), in which each of X1 and X2 are independently G, C, or absent, and X3 is T or C, or L-(G)n-L?, in which n is an integer of 5-9 inclusive, and L and L? are nucleotide segments having complementary sequences. Also provided herein are multimeric nucleic acid aptamers containing a backbone moiety, which comprises a palindromic sequence.

Abstract: A multi-processor system includes multiple processors arranged in multiple clusters. Different clusters have different power and performance characteristics. The system includes a task scheduler to schedule tasks to the processors. The task scheduler, in response to detection of a scheduling event trigger, is operative to identify a scheduling objective between a first objective of energy optimization and a second objective of load balance. The scheduling objective is identified based on at least respective operating frequencies and loading of all processors in a highest-capacity cluster of the multiple clusters. According to the identified scheduling objective, the task scheduler schedules a given task to a processor selected among the processors in the multiple clusters.

Abstract: System, apparatus, and method for extending network with power supply are disclosed. The apparatus includes a processing unit, a signal and power integration unit, a power supply unit, a transmission rate regulation unit, a display unit, and a symmetric transmission control unit. The signal and power integration unit integrates the electrical power with the data packages, so that the normal data transmission line can also transmit electrical power alone with signals to the electrical devices which are connected to the network extending apparatus. Therefore, the electrical devices do not need any extra power transmission line or independent power supply for obtaining the requisite power.

Abstract: System, apparatus, and method for extending network with power supply are disclosed. The apparatus includes a processing unit, a signal and power integration unit, a power supply unit, a transmission rate regulation unit, a display unit, and a symmetric transmission control unit. The signal and power integration unit integrates the electrical power with the data packages, so that the normal data transmission line can also transmit electrical power alone with signals to the electrical devices which are connected to the network extending apparatus. Therefore, the electrical devices do not need any extra power transmission line or independent power supply for obtaining the requisite power.