Patents by Inventor Chien-Hao Lu

Chien-Hao Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10861935
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
  • Publication number: 20200313920
    Abstract: A method for recording a multimedia call with common consent via an instant communication software program is proposed. Via execution of the software program, when an electronic device makes a multimedia call to another electronic device, a recording notification is provided to said another electronic device for notifying a user of said another electronic device that the multimedia call would be recorded. After the multimedia call has ended, one of the two electronic devices generates a recording file for the multimedia call, and transmits the recording file to a virtual chat room created for the two electronic devices.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 1, 2020
    Inventors: Chan-Guan KOH, Chun-Hao CHEN, Tzu-Ying WANG, Sheng-Yen FANG, Chien-Cheng LU, I-Yun CHAO
  • Publication number: 20200314043
    Abstract: A method for scheduled transmission of a message is to be implemented by an instant messaging (IM) device, and includes: executing IM software and providing a graphical user interface (GUI) which includes a chat interface for a chat session, the chat interface being established in advance by the IM software; when it is determined that a message is inputted in an input field of the chat interface and that a prearrangement icon of the chat interface is selected, presenting a date-and-time picker in the GUI for setting a scheduled time; generating a scheduled task when it is determined that the scheduled time has been set; and sending the message corresponding to the scheduled task to the chat session when it is determined that the scheduled time corresponding to the scheduled task has arrived.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 1, 2020
    Inventors: Chan-Guan KOH, Chun-Hao CHEN, Tzu-Ying WANG, Sheng-Yen FANG, Chien-Cheng LU, I-Yun CHAO
  • Publication number: 20200244809
    Abstract: A method of automatically playing a voice message is proposed to be implemented by a smartphone that executes an instant communication software program. The method includes: opening, by the smartphone, a chat window for communication between a user of the smartphone and a chatting target; and upon determining that there is at least one voice message not having been played before in the chat window and, based on a signal provided by a proximity sensor near a receiver of the smartphone, that there is an object close to the receiver, automatically and audibly outputting the at least one voice message using the receiver.
    Type: Application
    Filed: July 2, 2019
    Publication date: July 30, 2020
    Inventors: Chan-Guan KOH, Chun-Hao CHEN, Tzu-Ying WANG, Sheng-Yen FANG, Chien-Cheng LU, I-Yun CHAO
  • Publication number: 20200235292
    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MU) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin-Ren DAI, Chung-Ju LEE, Chung-Te LIN, Chih-Wei LU, Hsi-Wen TIEN, Tai-Yen PENG, Chien-Min LEE, Wei-Hao LIAO
  • Patent number: 10636963
    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ren Dai, Chung-Ju Lee, Chung-Te Lin, Chih-Wei Lu, Hsi-Wen Tien, Tai-Yen Peng, Chien-Min Lee, Wei-Hao Liao
  • Publication number: 20200052098
    Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
  • Patent number: 10534741
    Abstract: Example implementations relate to transmitting signals via USB ports. For example, a system according to the present disclosure, may include a host module including a plurality of USB ports, a first expansion module, and a second expansion module. The first expansion module may include a first USB port and a second USB port. The first expansion module may receive a signal from the host module at a first USB port, and direct the signal to a second USB port. The first expansion module may transmit the signal to a second expansion module via a second USB port.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 14, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chi So, Nam H Nguyen, Chien-Hao Lu, Roger D Benson
  • Publication number: 20190393325
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu
  • Publication number: 20190355816
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
  • Patent number: 10453943
    Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
  • Patent number: 10396063
    Abstract: In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Lee-Chung Lu, Yi-Kan Cheng, Sheng-Hsiung Chen, Po-Hsiang Huang, Shun Li Chen, Jeo-Yen Lee, Jyun-Hao Chang, Shao-Huan Wang, Chien-Ying Chen
  • Patent number: 10379589
    Abstract: An example disclosed herein is a non-volatile storage medium including instructions relating to control of power that, when executed by a processor, cause the processor to monitor a supply of power to a regulator, decouple supply of power to the regulator when the monitored supply of power is below a predetermined level, couple a power pack to the regulator to supply power to the regulator when the monitored supply of power is below the predetermined level, and generate an Advanced Configuration and Power Interface (ACPI) G1 Sleeping state signal when the monitored supply of power is below the predetermined level.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 13, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Patrick Ferguson, Chien-Hao Lu, Chih Liang Li, Szu Tao Tong
  • Patent number: 10374038
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I Kuo, Chii-Horng Li, Chia-Ling Chan, Li-Li Su, Yi-Fang Pai, Wei Te Chiang, Shao-Fu Fu, Wei Hao Lu
  • Patent number: 10312158
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Cheng Li, Chien-Hao Chen, Yung-Cheng Lu, Jr-Jung Lin, Chun-Hung Lee, Chao-Cheng Chen
  • Publication number: 20190165100
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Application
    Filed: March 15, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I KUO, Chii-Horng LI, Chia-Ling CHAN, Li-Li SU, Yi-Fang PAI, Wei Te CHIANG, Shao-Fu FU, Wei Hao LU
  • Publication number: 20190148633
    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
    Type: Application
    Filed: September 5, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ren DAI, Chung-Ju LEE, Chung-Te LIN, Chih-Wei LU, Hsi-Wen TIEN, Tai-Yen PENG, Chien-Min LEE, Wei-Hao LIAO
  • Publication number: 20190121772
    Abstract: Example implementations relate to transmitting signals via USB ports. For example, a system according to the present disclosure, may include a host module including a plurality of USB ports, a first expansion module, and a second expansion module. The first expansion module may include a first USB port and a second USB port. The first expansion module may receive a signal from the host module at a first USB port, and direct the signal to a second USB port. The first expansion module may transmit the signal to a second expansion module via a second USB port.
    Type: Application
    Filed: July 13, 2016
    Publication date: April 25, 2019
    Inventors: Chi So, Nam H Nguyen, Chien-Hao Lu, Roger D Benson
  • Patent number: 10101778
    Abstract: An example printed circuit board assembly (PCBA) includes a controller and a plurality of conductive contacts. The conductive contacts are coupled to the controller. The controller is to determine a type of chassis to which the PCBA is mounted.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: October 16, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Szu Tao Tong, Hsin-Tso Lin, Cheng-Yi Yang, Hai-Ling Hung, Chien-Hao Lu
  • Publication number: 20180120907
    Abstract: An example printed circuit board assembly (PCBA) includes a controller and a plurality of conductive contacts. The conductive contacts are coupled to the controller. The controller is to determine a type of chassis to which the PCBA is mounted.
    Type: Application
    Filed: May 28, 2015
    Publication date: May 3, 2018
    Inventors: Szu Tao Tong, Hsin-Tso Lin, Cheng-Yi Yang, Hai-Ling Hung, Chien-Hao Lu