Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.

Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.

Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.

Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.

Abstract: A circuit stack structure is provided. The circuit stack structure includes a conductor layer having metal wires arranged at intervals, propping portions respectively disposed in a gap between any two of the neighboring metal wires, and a protective layer covering the metal wires and the propping portions. The propping portions are electrically isolated with the metal wires. With supporting by the propping portions, all regions of a top surface of the protective layer corresponding to one of the propping portions are coplanar with all regions of the top surface of the protective layer corresponding to each of the metal wires.

Abstract: The present invention provides a pixel structure including a substrate, a thin-film transistor disposed on the substrate, a first insulating layer covering the thin-film transistor and the substrate, a common electrode, a connecting electrode, a second insulating layer, and a pixel electrode. The thin-film transistor includes a drain electrode. The first insulating layer has a first opening exposing the drain electrode. The common electrode and the connecting electrode are disposed on the first insulating layer. The connecting electrode extends into the first opening to be electrically connected to the drain electrode. The connecting electrode is electrically insulated from the common electrode. The second insulating layer covers the first insulating layer, the common electrode, the connecting electrode, and has a second opening exposing the connecting electrode. The pixel electrode is disposed on the second insulating layer and electrically connected to the connecting electrode through the second opening.

Abstract: A method for manufacturing pixel structure is provided. A patterned conductor layer including a gate, a scan line and a conductor pattern is formed on a substrate. A gate insulating layer, a metal oxide material layer and an etching stop material layer are formed on the substrate. Using the patterned conductor layer as mask, a patterned photoresist layer is formed on the etching stop material layer through a back exposure process. Using the patterned photoresist layer as mask, a metal oxide channel layer and an etching stop layer are formed above the gate. A source and a drain are formed on the etching stop layer. A passivation layer is formed on the substrate. A halftone mask is used to form a photosensitive layer on the passivation layer. The metal oxide material layer and the etching stop material layer on the scan line and the conductor pattern are removed.

Abstract: The present invention provides a pixel structure including a substrate, a thin-film transistor disposed on the substrate, a first insulating layer covering the thin-film transistor and the substrate, a common electrode, a connecting electrode, a second insulating layer, and a pixel electrode. The thin-film transistor includes a drain electrode. The first insulating layer has a first opening exposing the drain electrode. The common electrode and the connecting electrode are disposed on the first insulating layer. The connecting electrode extends into the first opening to be electrically connected to the drain electrode. The connecting electrode is electrically insulated from the common electrode. The second insulating layer covers the first insulating layer, the common electrode, the connecting electrode, and has a second opening exposing the connecting electrode. The pixel electrode is disposed on the second insulating layer and electrically connected to the connecting electrode through the second opening.

Abstract: A circuit stack structure is provided. The circuit stack structure includes a conductor layer having metal wires arranged at intervals, propping portions respectively disposed in a gap between any two of the neighboring metal wires, and a protective layer covering the metal wires and the propping portions. The propping portions are electrically isolated with the metal wires. With supporting by the propping portions, all regions of a top surface of the protective layer corresponding to one of the propping portions are coplanar with all regions of the top surface of the protective layer corresponding to each of the metal wires.

Abstract: A method for manufacturing pixel structure is provided. A patterned conductor layer including a gate, a scan line and a conductor pattern is formed on a substrate. A gate insulating layer, a metal oxide material layer and an etching stop material layer are formed on the substrate. Using the patterned conductor layer as mask, a patterned photoresist layer is formed on the etching stop material layer through a back exposure process. Using the patterned photoresist layer as mask, a metal oxide channel layer and an etching stop layer are formed above the gate. A source and a drain are formed on the etching stop layer. A passivation layer is formed on the substrate. A halftone mask is used to form a photosensitive layer on the passivation layer. The metal oxide material layer and the etching stop material layer on the scan line and the conductor pattern are removed.

Abstract: A display device and a fabrication method thereof are provided. The display device includes a first metal layer disposed on a display area and a peripheral area. An insulating layer covers the first metal layer. A patterned semiconductor layer is disposed on the insulating layer at the display area. A second metal layer is disposed on the patterned semiconductor layer and the insulating layer at the peripheral area. A transparent conductive layer directly covers the second metal layer. A protective layer completely covers the second metal layer, the patterned semiconductor layer and the transparent conductive layer. The protective layer includes a first portion, a second portion and a through hole, wherein the first portion has a height which is higher than a height of the second portion.

Abstract: An array substrate, liquid crystal display for the same and manufacturing method thereof are described. The array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of contact pads, a passivation layer and transparent conducting layer. The substrate has a first display region, a second display region and a first non-display region. The contact pads are disposed in the first non-display region. The transparent conducting layer disposed in the passivation layer includes a first pixel electrode, a second pixel electrode and a plurality of comb electrode. The first pixel electrode and second pixel electrode are disposed in the first display region and the second display region wherein the widths of the first pixel electrodes either are equal to or approximate the widths of the second pixel electrodes. The comb electrodes are disposed in the first non-display region and connected to the contact pads.

Abstract: A driven electrode structure of an in-plane switching liquid crystal display is divided into a plurality of sub-regions, each of the sub-regions includes a plurality of sub-driven electrodes, a plurality of intervals is formed between adjacent sub-driven electrodes, so as each of the sub-regions has the intervals, and at least two of the intervals in the sub-regions are different from one another. By changing the width or shape of each sub-driven electrode, at least two of the intervals in the sub-regions are different from one another, so as the Mura condition of the in-plane switching liquid crystal display can be obscure, so as the Mura defect can be minimized uniformly without being visually recognized by human eyes and further improve the visual defect of the Mura.

Abstract: An organic electroluminescent display device includes a bottom substrate, a covering substrate, a pixel controlling unit, a first organic light emitting unit, and a second organic light emitting unit. The covering substrate is disposed oppositely to the bottom substrate. The pixel controlling unit is disposed between the bottom substrate and the covering substrate. The first organic light emitting unit is disposed between the pixel controlling unit and the covering substrate. The second organic light emitting unit is disposed between the pixel controlling unit and the bottom substrate. The pixel controlling unit is electrically connected to the first organic light emitting unit and the second organic light emitting unit.