Abstract: In 5GS, Single-Network Slice Selection Assistance Information (S-NSSAI) based backoff (BO) timers (T3584/T3585) can be applied to either the registered PLMN or all the PLMNs based on a 5GSM congestion re-attempt indicator. For a specific PDU session, the corresponding BO timer applied to the registered PLMN and the BO timer applied to all PLMN can be both running concurrently. It is proposed for a UE to stop both the BO timer applied to all the PLMNs and the BO timer applied to the registered PLMN, if running, in all the following scenarios: 1) Receiving a PDU session release command without a BO timer, 2) Receiving a PDU session release command with 5GSM cause #39, 3) Receiving a PDU session modification command, 4) Receiving a 5GSM message with a 5GSM congestion control BO timer value, and 5) Receiving a PDU session authentication command.

Abstract: An operation method for a memory device is provided. The memory device includes a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector. The method includes providing a voltage pulse to the memory device. A voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector. A voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is raised for reducing threshold voltage drift of the two-terminal selector.

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.

Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.

Abstract: A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.

Abstract: A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.