Abstract: A multi-chip integrated package design system includes a model analysis, a 3D model analysis and an electrical simulation. The model analysis obtains a pin connection mode of the designed circuit according to a designed circuit, obtains at least one conductive layer of the designed circuit according to a layer stackup, selects a transmission line model that meets the pin connection mode and at least one conductive layer, substitutes the layer stackup and a design rule into the selected transmission line model to generate an equivalent circuit, generates a corresponding relationship according to the equivalent circuit, and obtains the transmission line length corresponding to a parameter design target according to the corresponding relationship. The 3D model analysis constructs a 3D model of the designed circuit according to the obtained the transmission line length. The electrical simulation determines whether the characteristic parameter of the 3D model meets the parameter design target.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic component is disposed on a substrate and covered with an encapsulation layer, and a frame body is embedded in the encapsulation layer and protrudes from the substrate. Therefore, the frame body can disperse thermal stress, thereby preventing warping from occurring to the electronic package.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: A semiconductor processing system is provided. The semiconductor processing system includes a first chamber arranged to perform a first semiconductor process; a second chamber arranged to perform a second semiconductor process; a cooling chamber having a pedestal; and a plurality of non-contact temperature sensors mounted in the cooling chamber, and arranged to measure a temperature of a wafer disposed on the pedestal. In one aspect, the first chamber is arranged to transfer the wafer to the cooling chamber upon completion of the first semiconductor process in the first chamber. In another aspect, the cooling chamber is arranged to measure the temperature of the wafer in the cooling chamber and arranged to transfer the wafer to the second chamber when the temperature of wafer is at a target temperature, or pause processing of the wafer when the temperature of the wafer is not at the target temperature.

Abstract: The thin film deposition system includes: a deposition chamber, a precursor source container containing a precursor source; and a precursor conduit. The precursor conduit is elongated and extends between a proximate end and a distal end, and the proximate end is coupled to an outlet of the precursor source container, and the distal end is coupled to an inlet of the deposition chamber.

Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.

Abstract: A circuit of a resonant power converter comprising: a high-side switch and a low-side switch, coupled to form a half-bridge switching circuit which is configured to switch a transformer for generating an output voltage; a high-side drive circuit, generating a high-side drive signal coupled to drive the high-side switch in response to a high-side control signal; a bias voltage, coupled to a bootstrap diode and a bootstrap capacitor providing a power source from the bootstrap capacitor for the high-side drive circuit; wherein the high-side drive circuit generates the high-side drive signal with a fast slew rate to turn on the high-side switch when the high-side switch is to be turned on with soft-switching; the high-side drive circuit generates the high-side drive signal with a slow slew rate to turn on the high-side switch when the high-side switch is to be turned on without soft-switching.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, then a cladding layer is formed to cover the electronic element, and a shielding layer is formed on the cladding layer to cover the electronic element. The cladding layer is bonded to a shielding structure, and the shielding structure is located between the shielding layer and the electronic element, so as to prevent the electronic element from being subjected to external electromagnetic interference via multiple shielding mechanisms of the shielding structure and the shielding layer.

Abstract: A display driver circuit for high resolution and high frame rate and a display device using the same are provided. A display driver circuit for high resolution and high frame rate includes a GAMMA output circuit, multiple digital-to-analog converters (DACs), multiple source operation amplifiers and at least a pre-charging circuit. The GAMMA output circuit outputs multiple grayscales of GAMMA voltages. Each DAC receives the GAMMA voltages and provides an output data voltage according to display data. Input terminals of the source operation amplifiers correspondingly coupled to output terminals of the DACs receive the corresponding output data voltages. The pre-charging circuit coupled between the input terminal of at least one of the source operation amplifiers and the output terminal of at least one of the DACs pre-charges the input terminal of the coupled source operation amplifier, so that an output terminal of the coupled source operation amplifier has fast response to the received output data voltage.