Abstract: Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures formed in an array disposed over the gate electrode; and a second protection structure comprising a ring shape from a top-view perspective, and disposed over the gate dielectric layer and at a same level as the plurality of first protection structures from a cross-sectional view.

Abstract: A touch sensor includes a substrate, sensing channels, and a protective layer. The sensing channels are disposed at intervals on a surface of the substrate, and any one of the sensing channels includes an electrode portion and a silver trace portion electrically connected to the electrode portion. The protective layer is disposed on the substrate and covers and encapsulates the sensing channels. After the touch sensor is subjected to a salt spray test with sodium chloride solution of a mass percentage concentration of 5% at a rate of 1 mL/H to 2 mL/H under an ambient temperature of 35° C. for 48 hours, a resistance change rate of any one of the sensing channels is less than or equal to 10%, and a resistance distribution difference between the sensing channels is less than or equal to 10%.

Abstract: The present application provides an overlay measuring apparatus, adapted to determine relative positions of two or more successive patterned layers of a device. The overlay measuring apparatus includes a stage and an imaging assembly. The device is placed on the stage. The imaging assembly includes a plurality of optical heads and a plurality of overlay marks assembled on the optical heads. The relative positions of the two or more successive patterned layers of the device are determined using light reflected from the device and passing through the overlay mark mounted on the respective optical head.

Abstract: The present application provides an overlay measuring apparatus, adapted to determine relative positions of two or more successive patterned layers of a device. The overlay measuring apparatus includes a stage and an imaging assembly. The device is placed on the stage. The imaging assembly includes a plurality of optical heads and a plurality of overlay marks assembled on the optical heads. The relative positions of the two or more successive patterned layers of the device are determined using light reflected from the device and passing through the overlay mark mounted on the respective optical head.

Abstract: The present application provides an optical system and a method of operating an overlay measuring apparatus. The overlay measuring apparatus is adapted to determine relative positions of two or more successive patterned layers of a device. The overlay measuring apparatus includes a stage and an imaging assembly. The device is placed on the stage. The imaging assembly includes a plurality of optical heads and a plurality of overlay marks assembled on the optical heads. The relative positions of the two or more successive patterned layers of the device are determined using light reflected from the device and passing through the overlay mark mounted on the respective optical head.