Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.

Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

Abstract: A method and a system for detecting and analyzing a mucosa of a digestive tract are provided. The method includes detecting reply signals from the mucosa of the digestive tract within a depth range, acquiring 2D vascular images by performing a vascular enhancement on the reply signals, constructing a 3D vascular contrasting image of at least part of the mucosa of the digestive tract within the depth range by recombining at least part of the 2D vascular images, and reconstructing a 3D vascular contrasting projection image by performing a projection process to the 3D vascular contrasting image, and defining a stage of the mucosa of the digestive tract within the depth range according to the 3D vascular contrasting projection image, the 3D vascular contrasting image, the 2D vascular images, and vessel morphologies shown therein.

Abstract: A pixel structure includes a switch element on a substrate, a first electrode, and a second electrode. The first electrode includes first to third trunk portions and first to fourth branch portions. The third trunk portion is located between the first and second trunk portions. The first branch portions are connected to the first trunk portion. The second and third branch portions are connected to the third trunk portion. The fourth branch portions are connected to the second trunk portion. The second electrode includes fourth and fifth trunk portions and the fifth to eighth branch portions. The fourth trunk portion overlaps a gap between the first and second branch portions. The fifth trunk portion overlaps a gap between the third and fourth branch portions. The fifth and sixth branch portions are connected to the fourth trunk portion. The seventh and eighth branch portions are connected to the fifth trunk portion.

Abstract: A pixel structure includes a switch element on a substrate, a first electrode, and a second electrode. The first electrode includes first to third trunk portions and first to fourth branch portions. The third trunk portion is located between the first and second trunk portions. The first branch portions are connected to the first trunk portion. The second and third branch portions are connected to the third trunk portion. The fourth branch portions are connected to the second trunk portion. The second electrode includes fourth and fifth trunk portions and the fifth to eighth branch portions. The fourth trunk portion overlaps a gap between the first and second branch portions. The fifth trunk portion overlaps a gap between the third and fourth branch portions. The fifth and sixth branch portions are connected to the fourth trunk portion. The seventh and eighth branch portions are connected to the fifth trunk portion.

Abstract: A method and a system for detecting and analyzing a mucosa of a digestive tract are provided. The method includes detecting reply signals from the mucosa of the digestive tract within a depth range, acquiring 2D vascular images by performing a vascular enhancement on the reply signals, constructing a 3D vascular contrasting image of at least part of the mucosa of the digestive tract within the depth range by recombining at least part of the 2D vascular images, and reconstructing a 3D vascular contrasting projection image by performing a projection process to the 3D vascular contrasting image, and defining a stage of the mucosa of the digestive tract within the depth range according to the 3D vascular contrasting projection image, the 3D vascular contrasting image, the 2D vascular images, and vessel morphologies shown therein.

Abstract: A multi-ported memory that supports multiple read and write accesses is described. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for read operation(s) and write operation(s) to be received during the same clock cycle. In the event that an incoming write operation is blocked by read operation(s), data for that write operation may be stored in one of a plurality of cache banks included in the multi-port memory. The cache banks are accessible to both write and read operations. In the event than the write operation is not blocked by read operation(s), a determination is made as to whether data for that incoming write operation is stored in the memory bank targeted by that incoming write operation or in one of the cache banks.

Abstract: A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

Abstract: A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

Abstract: Disclosed are various embodiments that provide serial replication of multicast packets by performing a first data fetch to fetch first data from a memory buffer, the first data comprising a first packet pointer representing a first packet and a replication number indication a number of times the first packet is to be replicated. Furthermore, various embodiments are directed to performing a second data fetch to fetch second data from a memory buffer, the second data comprising a first packet pointer representing a second packet and serially replicating the first packet and the second packet based at least in part upon the replication number and a predetermined threshold value.