Abstract: A light box structure includes a bracket and a board. The bracket is in an arc shape and has a first surface and a second surface opposite to each other. The board has a plurality of magnetic positioning posts. The magnetic positioning posts have at least two different heights. The board is attracted and attached on the first surface of the bracket through the magnetic positioning posts.

Abstract: A light box structure includes a bracket and a board. The bracket is in an arc shape and has a first surface and a second surface opposite to each other. The board has a plurality of magnetic positioning posts. The magnetic positioning posts have at least two different heights. The board is attracted and attached on the first surface of the bracket through the magnetic positioning posts.

Abstract: The present invention relates to a method for manufacturing a triple cross-linked collagen, which comprises the following steps: providing a soluble collagen sample; mixing the collagen sample with a first cross-linking agent to form a one cross-linked collagen; mixing the first cross-linked collagen with a second cross-linking agent to form a second cross-linked collagen; and mixing the second cross-linked collagen with a third cross-linking agent to form a triple cross-linked collagen, wherein each of the first cross-linking agent, the second cross-linking agent, and the third cross-linking agent is selected from the group consisting of an aldehyde cross-linking agent, an imine cross-linking agent, and an epoxide cross-linking agent. In addition, the first cross-linking agent is different form the second cross-linking agent, and the third cross-linking agent is different form the first cross-linking agent and the second cross-linking agent.

Abstract: The present invention relates to a method for manufacturing a triple cross-linked collagen, which comprises the following steps: providing a soluble collagen sample; mixing the collagen sample with a first cross-linking agent to form a one cross-linked collagen; mixing the first cross-linked collagen with a second cross-linking agent to form a second cross-linked collagen; and mixing the second cross-linked collagen with a third cross-linking agent to form a triple cross-linked collagen, wherein each of the first cross-linking agent, the second cross-linking agent, and the third cross-linking agent is selected from the group consisting of an aldehyde cross-linking agent, an imine cross-linking agent, and an epoxide cross-linking agent. In addition, the first cross-linking agent is different form the second cross-linking agent, and the third cross-linking agent is different form the first cross-linking agent and the second cross-linking agent.

Abstract: A pixel-data processing circuit delivers a fixed number of pixels to a video processing stage using an irregular sampling pattern that is defined by a variably-definable sampling window. In one example embodiment directed to processing an input stream of pixels corresponding to an array of video pixels, the window size is selected from one of various options for sampling subsets of the array as a two-dimensional window that spans the pixels in the array. A sampling-window is used such that the window size is a multiple of the sampling-window size and the sampling-window size defines the fixed number of pixels.

Abstract: Artifact detection and counting is enhanced using looping in both the horizontal and vertical direction is enhanced via a reduced bandwidth for accumulation of count values into count table entries. According to an example embodiment of the present invention, first and second loops are made for horizontal and vertical count table entries. Quotient and remainder values of a detected artifact value are used for increasing count table entries in the first looping pass, and the count table entries are increased using the quotient value in the second loop. The table increase in the first loop is limited to the length of the remainder value, and the table increase in the second loop is limited to the length of the row or column in the count table being used. In this manner, latency for additions to the count table and the bandwidth for making the additions are reduced, relative to conventional applications. In addition, each entry into the table can be reduced to one addition.

Abstract: Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

Abstract: According to an example embodiment, the present invention is directed to pixel-data processing that includes scanning a first 2×2 line in each of a series of immediately adjacent pixel blocks, prior to scanning a second 2×2 line in each of the series of pixel blocks. Each scanned line is then processed for motion compensation in a manner that addresses challenges, including those discussed above, related to buffer size requirements, power consumption requirements and latency.

Abstract: Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

Abstract: Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

Abstract: Methods and apparatuses for run length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor in response to the microprocessor receiving a single instruction includes: receiving a first list of a plurality of elements from a first vector register; generating a plurality of run values respectively for the first list of elements, at least one of the plurality of run values indicating the number of consecutive elements of a first value immediately preceding the corresponding element in the first list; and outputting the plurality of run values into a second vector register; where the above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle.

Abstract: Methods and apparatuses for concatenating codewords of variable lengths using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to pack bit streams of variable lengths including: receiving a first bit segment from a first vector register; receiving a second bit segment from a second vector register; determining whether or not the sum of the bit length of the first bit segment and the bit length of the second bit segment is larger than a required length; generating a third bit segment from the first and second bit segments; and outputting the third bit segment in a third vector register; where the above operations are performed in response to the microprocessor receiving a first single instruction.

Abstract: Methods and apparatuses for concatenating codewords of variable lengths using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to concatenate codewords of variable lengths includes: receiving a plurality of codewords from a first vector register; receiving a plurality of lengths representing bit lengths of the plurality of codewords respectively; generating a first bit stream from concatenating the plurality of codewords; summing the plurality of lengths to generate the bit length of the first bit stream; and outputting the first bit stream and the first length; wherein the above operations are performed in response to the microprocessor receiving a single instruction.

Abstract: According to an example embodiment, the present invention is directed to pixel-data processing that includes scanning a first 2×2 line in each of a series of immediately adjacent pixel blocks, prior to scanning a second 2×2 line in each of the series of pixel blocks. Each scanned line is then processed for motion compensation in a manner that addresses challenges, including those discussed above, related to buffer size requirements, power consumption requirements and latency.

Abstract: A pixel-data processing circuit delivers a fixed number of pixels to a video processing stage using an irregular sampling pattern that is defined by a variably-definable sampling window. In one example embodiment directed to processing an input stream of pixels corresponding to an array of video pixels, the window size is selected from one of various options for sampling subsets of the array as a two-dimensional window that spans the pixels in the array. A sampling-window is used such that the window size is a multiple of the sampling-window size and the sampling-window size defines the fixed number of pixels.

Abstract: Artifact detection and counting is enhanced using looping in both the horizontal and vertical direction is enhanced via a reduced bandwidth for accumulation of count values into count table entries. According to an example embodiment of the present invention, first and second loops are made for horizontal and vertical count table entries. Quotient and remainder values of a detected artifact value are used for increasing count table entries in the first looping pass, and the count table entries are increased using the quotient value in the second loop. The table increase in the first loop is limited to the length of the remainder value, and the table increase in the second loop is limited to the length of the row or column in the count table being used. In this manner, latency for additions to the count table and the bandwidth for making the additions are reduced, relative to conventional applications. In addition, each entry into the table can be reduced to one addition.

Abstract: A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle.

Abstract: A vertical signal processing circuit including a buffer and a polyphase filter, and adapted to simultaneously process vertical peaking and vertical scaling on pixel data in a first operational mode. In a first operational vertical peaking and scaling mode, the embodiment includes receiving pixel data at a first rate, circulating the data in line buffers and filtering the circulated data through a polyphase filter configured with coefficients derived by convolving peaking filter coefficients with scaling polyphase filter coefficients, and presenting processed pixel data for storage at a second, different pixel rate. Using a control circuit, the pixel-data processing circuit can switch between operational modes by setting different coefficients for the polyphase filter circuit.

Abstract: The present invention provides a novel semi-synthetic method of producing a variety of novel taxane derivatives. The method involves the reaction of a phenylisoserine derivative with a suitably blocked Baccatin III derivative to produce a taxane substrate that may be further modified to form Pactitaxel and other potentially useful taxane derivatives.