Patents by Inventor Chien-Hsing Cheng

Chien-Hsing Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160099306
    Abstract: A monolithic merged PIN Schottky (MPS) diode including a chip, at least one PIN diode, at least one Schottky diode and a termination structure is provided. The chip has a first active area, a second active area and a termination area. The PIN diode is disposed in the first active area. The Schottky diode is disposed in the second active area. The termination structure is disposed in the termination area. The first active area and the second active area are separated by the termination area. The PIN diode and the Schottky diode share the termination structure.
    Type: Application
    Filed: June 4, 2015
    Publication date: April 7, 2016
    Inventor: Chien-Hsing Cheng
  • Publication number: 20150137697
    Abstract: An integrated light source driving circuit including a power transistor, a driving chip and a diode and a light source module using the same are provided. The power transistor includes a substrate, first and second active regions, a gate region and an isolation region. The first and second active regions are disposed on two opposite sides of the substrate. The second active region and the gate region are disposed on the same side of the substrate. The isolation region is electrically connected to the first active region and electrically independent with/from the second active region and the gate region. The driving chip is stacked on the second active region and electrically connected to the gate region. The diode is disposed in the isolation region of the power transistor, where an anode of the diode is disposed toward the isolation region to be electrically connected to the first active region.
    Type: Application
    Filed: July 3, 2014
    Publication date: May 21, 2015
    Inventor: Chien-Hsing Cheng
  • Publication number: 20140353747
    Abstract: A trench gate MOSFET is provided. An N-type epitaxial layer is disposed on an N-type substrate. An N-type source region is disposed in the N-type epitaxial layer. The N-type epitaxial layer has at least one trench therein. An insulating layer serving as a gate insulating layer is disposed in the trench. A conductive layer serving as a gate fills up the trench. Two isolation structures are disposed in the N-type source region beside the trench and contact the trench. Two conductive plugs are disposed in the N-type epitaxial layer beside the trench and penetrate through the N-type source region. A dielectric layer is disposed on the N-type epitaxial layer. A metal layer is disposed on the dielectric layer and electrically connected to the N-type source region.
    Type: Application
    Filed: February 26, 2014
    Publication date: December 4, 2014
    Applicant: BEYOND INNOVATION TECHNOLOGY CO., LTD.
    Inventor: Chien-Hsing Cheng
  • Publication number: 20140159144
    Abstract: A trench gate MOSFET is provided. An N-type epitaxial layer on an N-type substrate has a wider first trench and a narrower second trench below the first trench. A first insulating layer is in the second trench. First and second conductive layers are respectively in lower and upper portions of the first trench. A thicker second insulating layer is between the first conductive layer and N-type epitaxial layer and between the first insulating layer and first conductive layer, and a thinner third insulating layer is between the second conductive layer and N-type epitaxial layer. A P-type first doped region is in the N-type epitaxial layer below the first trench and surrounds the top of the second trench. A P-type second doped region is in the N-type epitaxial layer below the second trench. A source region is in the N-type epitaxial layer and surrounds the top of the first trench.
    Type: Application
    Filed: September 16, 2013
    Publication date: June 12, 2014
    Applicant: Beyond Innovation Technology Co., Ltd.
    Inventor: Chien-Hsing Cheng
  • Patent number: 8669614
    Abstract: A monolithic metal oxide semiconductor field effect transistor (MOSFET)-Schottky diode device including a chip, a MOSFET, a Schottky diode and a termination structure is provided. The chip is divided into a transistor region, a diode region and a termination region. The MOSFET is disposed on the transistor region. The Schottky diode is disposed on the diode region. The termination structure is disposed on the termination region. The transistor region and the diode region are divided by the termination region. The MOSFET and Schottky diode share the termination structure.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: March 11, 2014
    Assignee: Beyond Innovation Technology Co., Ltd.
    Inventor: Chien-Hsing Cheng
  • Publication number: 20120292695
    Abstract: A monolithic metal oxide semiconductor field effect transistor (MOSFET)-Schottky diode device including a chip, a MOSFET, a Schottky diode and a termination structure is provided. The chip is divided into a transistor region, a diode region and a termination region. The MOSFET is disposed on the transistor region. The Schottky diode is disposed on the diode region. The termination structure is disposed on the termination region. The transistor region and the diode region are divided by the termination region. The MOSFET and Schottky diode share the termination structure.
    Type: Application
    Filed: January 13, 2012
    Publication date: November 22, 2012
    Applicant: BEYOND INNOVATION TECHNOLOGY CO., LTD.
    Inventor: Chien-Hsing Cheng
  • Patent number: 7843017
    Abstract: A transistor having a start-up control element is provided. The transistor includes an N-type depletion mode transistor and an N-type enhancement mode transistor. The N-type depletion mode transistor includes a drain for electrically connecting to an external power supply, and a gate normally grounded. The N-type enhancement mode transistor includes a drain electrically connected to the external power supply, and a gate electrically connected to a source of the depletion mode transistor.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 30, 2010
    Assignee: Richtek Technology Corporation
    Inventors: Chien-Hsing Cheng, Kuang-Ming Chang
  • Publication number: 20080290841
    Abstract: The present invention discloses a charging circuit for charging a bootstrap capacitor from a supply voltage, the charging circuit comprising: a depletion mode transistor, having a first end of its source/drain electrically connected with the supply voltage, a gate electrically connected to the supply voltage, and a second end of its source/drain electrically connected with the bootstrap capacitor. Preferably, a diode is provided between the supply voltage and the depletion mode transistor.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Inventors: Kuang-Ming Chang, Chien-Hsing Cheng
  • Publication number: 20080073675
    Abstract: A transistor having a start-up control element is provided. The transistor includes an N-type depletion mode transistor and an N-type enhancement mode transistor. The N-type depletion mode transistor includes a drain for electrically connecting to an external power supply, and a gate normally grounded. The N-type enhancement mode transistor includes a drain electrically connected to the external power supply, and a gate electrically connected to a source of the depletion mode transistor.
    Type: Application
    Filed: January 24, 2007
    Publication date: March 27, 2008
    Inventors: Chien-Hsing Cheng, Kuang-Ming Chang