Patents by Inventor Chien-Hsing Li

Chien-Hsing Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240362387
    Abstract: A device includes a first conductive line as an input line. The device further includes a second conductive line as an output line, wherein the first conductive line and the second conductive line are in a same level of the integrated circuit. The device further includes a first passive isolation structure between the first conductive line and the second conductive line, wherein the first passive isolation structure and the second conductive line are each positioned at an integer multiple of an interval between the first conductive line and the first passive isolation structure.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Cheok-Kei LEI, Jerry Chang Jui KAO, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chien-Hsing LI
  • Patent number: 12073162
    Abstract: A method of modifying an integrated circuit layout includes determining whether a first conductive line and a second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold. The method further includes adjusting the integrated circuit layout by moving the first conductive line in the integrated circuit layout in response to determining to move the first conductive line. The method further includes inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li
  • Publication number: 20240243664
    Abstract: A controller of a buck-boost conversion circuit and a mode switching method thereof are provided. The controller control operations of multiple switches of the buck-boost conversion circuit to convert an input voltage into an output voltage and provide an output current. The controller includes a slope compensation circuit, a control loop, and a mode switching circuit. The slope compensation circuit generates a slope compensation signal according to a mode switching signal of a current cycle. The control loop is coupled to the slope compensation circuit and the switches respectively, and is configured to generate multiple switch control signals according to the slope compensation signal, a feedback voltage related to the output voltage, and a current sense signal related to the output current to control the operations of the switches respectively. The mode switching circuit is coupled to the slope compensation circuit and the control loop.
    Type: Application
    Filed: December 22, 2023
    Publication date: July 18, 2024
    Applicant: uPI Semiconductor Corp.
    Inventors: Yen Hui Wang, Yi-Xian Jan, Chien Hsien Tsai, Kuo-Jen Kuo, Chao-Chung Huang, Cheng-Hsing Li
  • Publication number: 20230090213
    Abstract: A method of modifying an integrated circuit layout includes determining whether a first conductive line and a second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold. The method further includes adjusting the integrated circuit layout by moving the first conductive line in the integrated circuit layout in response to determining to move the first conductive line. The method further includes inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line.
    Type: Application
    Filed: November 30, 2022
    Publication date: March 23, 2023
    Inventors: Cheok-Kei LEI, Jerry Chang Jui KAO, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chien-Hsing LI
  • Patent number: 11526649
    Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li
  • Patent number: 11074390
    Abstract: A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien-Hsing Li, Ting-Wei Chiang, Jung-Chan Yang, Ting Yu Chen
  • Publication number: 20210200927
    Abstract: A system and method for transistor placement in a standard cell layout includes identifying a plurality of transistors in a circuit. A drain terminal of each of the plurality of transistors is connected to an output of the circuit. The system and method also include determining that a first transistor and a second transistor of the plurality of transistors satisfy a merging priority, combining an active region of the first transistor and the second transistor to form a mega transistor having a common active region, and replacing the first transistor and the second transistor in the standard cell layout of the circuit with the mega transistor. The common active region combines the active region of a first drain terminal of the first transistor and a second drain terminal of the second transistor.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: Cheok-Kei Lei, Chi-Lin Liu, Yu-Lun Ou, Chien-Hsing Li, Zhe-Wei Jiang, Hui-Zhong Zhuang
  • Publication number: 20210192118
    Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Cheok-Kei LEI, Jerry Chang Jui KAO, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chien-Hsing LI
  • Patent number: 10943050
    Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li
  • Publication number: 20200134130
    Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.
    Type: Application
    Filed: July 17, 2019
    Publication date: April 30, 2020
    Inventors: Cheok-Kei LEI, Jerry Chang Jui KAO, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chien-Hsing LI
  • Publication number: 20200104450
    Abstract: A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.
    Type: Application
    Filed: July 15, 2019
    Publication date: April 2, 2020
    Inventors: Chien-Hsing LI, Ting-Wei CHIANG, Jung-Chan YANG, Ting Yu CHEN
  • Patent number: 9440387
    Abstract: A heating apparatus for a nozzle of an injection machine includes a helical-spring shaped heating portion, a first sleeve, and a second sleeve. The first sleeve includes a first blocking portion and forms internal threads. The second sleeve includes a second blocking portion and forms external threads. The heating portion is received in the second sleeve. The internal threads are screwed into the external threads. The first blocking portion and the second blocking portion sandwich the heating portion.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: September 13, 2016
    Assignee: FOXNUM TECHNOLOGY CO., LTD.
    Inventors: Chien-Hsing Li, Cheng-Wei Weng
  • Publication number: 20140319126
    Abstract: A heating apparatus for a nozzle of an injection machine includes a helical-spring shaped heating portion, a first sleeve, and a second sleeve. The first sleeve includes a first blocking portion and forms internal threads. The second sleeve includes a second blocking portion and forms external threads. The heating portion is received in the second sleeve. The internal threads are screwed into the external threads. The first blocking portion and the second blocking portion sandwich the heating portion.
    Type: Application
    Filed: November 28, 2013
    Publication date: October 30, 2014
    Applicant: FOXNUM TECHNOLOGY CO., LTD.
    Inventors: CHIEN-HSING LI, CHENG-WEI WENG
  • Patent number: 8851876
    Abstract: An injection mold includes a first plate, a second plate, a movable plate, a ball screw, a ball nut, an injection screw, a transmission shaft, an injection motor, a metering motor, a first driving assembly and a second driving assembly. The ball screw is rotatably supported by the first plate. The ball nut is fixed to the movable plate, and is threadedly engaged with the ball screw. The injection screw is coaxially positioned with the ball screw. The transmission shaft is rotatably supported by the second plate. The injection motor is fixedly mounted on the first plate. The metering motor is fixed mounted on the second plate. The first driving assembly is connected to the injection motor to drive the ball screw. The second driving assembly is connected to the metering motor to rotate the transmission shaft for moving the injection screw.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 7, 2014
    Assignee: Foxnum Technology Co., Ltd.
    Inventors: Yu-Ta Chen, Chien-Hsing Li
  • Publication number: 20130108729
    Abstract: An injection mold includes a first plate, a second plate, a movable plate, a ball screw, a ball nut, an injection screw, a transmission shaft, an injection motor, a metering motor, a first driving assembly and a second driving assembly. The ball screw is rotatably supported by the first plate. The ball nut is fixed to the movable plate, and is threadedly engaged with the ball screw. The injection screw is coaxially positioned with the ball screw. The transmission shaft is rotatably supported by the second plate. The injection motor is fixedly mounted on the first plate. The metering motor is fixed mounted on the second plate. The first driving assembly is connected to the injection motor to drive the ball screw. The second driving assembly is connected to the metering motor to rotate the transmission shaft for moving the injection screw.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 2, 2013
    Applicant: FOXNUM TECHNOLOGY CO., LTD.
    Inventors: YU-TA CHEN, CHIEN-HSING LI
  • Patent number: 7042322
    Abstract: A high-performance liquid magnetizer including a powerful magnet and a fluid sink. A spiral fluid guide being disposed in the fluid sink. A first opening disposed at the center of the sink and a second opening on one side of the fluid guide. The liquid flowing through the first opening into the fluid guide towards the second opening. The spiral sink extending the magnetization time for the fluid while the revolving direction of the liquid help improve the magnetism field effects.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: May 9, 2006
    Inventor: Chien-Hsing Li
  • Publication number: 20050219024
    Abstract: A high-performance liquid magnetizer including a powerful magnet and a fluid sink. A spiral fluid guide being disposed in the fluid sink. A first opening disposed at the center of the sink and a second opening on one side of the fluid guide. The liquid flowing through the first opening into the fluid guide towards the second opening. The spiral sink extending the magnetization time for the fluid while the revolving direction of the liquid help improve the magnetism field effects.
    Type: Application
    Filed: April 2, 2004
    Publication date: October 6, 2005
    Inventor: Chien-Hsing Li
  • Publication number: 20050019679
    Abstract: A method of fabricating a color filter substrate is described. A black matrix is formed on a substrate. A color photoresist is formed for covering the black matrix. A photomask is located over the substrate, and then an exposure process is performed. The photomask comprises a transparent region, a partial transparent region and a no-transparent region, wherein the partial transparent region is located between the transparent region and the no-transparent region and is also located at the edge of the black matrix. A development process is performed for patterning the color photoresist. Since the exposure process is performed with the photomask via the partial transparent region, the issue that the height difference exists at the edge of the black matrix due to using black resin can be resolved.
    Type: Application
    Filed: March 25, 2004
    Publication date: January 27, 2005
    Inventors: Wen-Chin Lo, Chien-Hsing Li, Liang-Jen Lin
  • Publication number: 20040069017
    Abstract: A display element has a luminescent body formed on a glass substrate, a glass cap with the rim bonded to the rim of the glass substrate, and a sealing layer of frit formed on the bonding region between the glass substrate and the glass cap. In encapsulating, the display element is placed between a pedestal an a pressing plate, and then a high-power laser beam is provided to penetrate the glass cap to focus on the sealing layer, resulting in sintering frit. Also, pressure is applied to the pedestal and the pressing plate.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 15, 2004
    Applicant: DELTA OPTOELECTRONICS INC.
    Inventors: Chien-Hsing Li, Chun-Chien Chen, Jiun-Wei Tsai, Cheng-Nan Yeh, Lai-Cheng Chen
  • Patent number: 6631565
    Abstract: An alignment tool for assembling a rear plate and a frame of a flat display panel is introduced. The rear plate includes a front surface, a rear surface opposing to the front surface for adhering with the frame in an aligning process, and an alignment mark located at the front surface. The alignment mark has a predetermined thickness and is protruded from the front surface. The alignment tool includes a base, a clamp arm and an upper arm. The base further includes a base top surface and an alignment notch. The base top surface is used for contacting with the front surface of the rear plate and the alignment notch has at least two alignment sides for matching with the alignment mark. The clamp arm is protruded from the base, and the upper arm is protruded from the clamp arm and used for aligning with the frame. The upper arm includes an arm lower surface parallel to and spaced apart from the base top surface by a predetermined distance for forming an open space in between.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: October 14, 2003
    Assignee: Acer Display Technology, Inc.
    Inventors: Jiun Ham Wu, Chien-Hsing Li, Po-Cheng Chen