Abstract: A wafer acceptance test (WAT) system and method that, in one embodiment, includes: (1) a saturation current WAT subsystem operable to generate a weighted standard deviation based on target NMOS and PMOS saturation currents and saturation current WAT results, (2) a wafer IC speed WAT subsystem operable to generate a speed performance probability distribution of wafer ICs based on the weighted standard deviation and speed WAT results, (3) a wafer IC power WAT subsystem operable to employ the speed WAT results and power WAT results to generate a power performance model of wafer ICs, and (4) a yield calculator operable to generate a power performance variance probability distribution of wafer ICs based on the power performance model and the power WAT results, and to employ the speed performance probability distribution and the power performance variance probability distribution to generate the yield forecast with respect to a target performance profile.

Abstract: A wafer acceptance test (WAT) system and method that, in one embodiment, includes: (1) a saturation current WAT subsystem operable to generate a weighted standard deviation based on target NMOS and PMOS saturation currents and saturation current WAT results, (2) a wafer IC speed WAT subsystem operable to generate a speed performance probability distribution of wafer ICs based on the weighted standard deviation and speed WAT results, (3) a wafer IC power WAT subsystem operable to employ the speed WAT results and power WAT results to generate a power performance model of wafer ICs, and (4) a yield calculator operable to generate a power performance variance probability distribution of wafer ICs based on the power performance model and the power WAT results, and to employ the speed performance probability distribution and the power performance variance probability distribution to generate the yield forecast with respect to a target performance profile.

Abstract: A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces.

Abstract: A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb5Ge3O11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb5Ge3O11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.

Abstract: A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents.

Abstract: A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents.

Abstract: A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.

Abstract: A method of forming the FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel, which extends into the drain junction region. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region.

Abstract: The structure of a c-axis FEM cell semiconductor includes a silicon substrate; a source junction region and a drain junction region located in the substrate; a gate junction region located between the source junction region and the drain junction region; a FEM gate unit including a lower electrode, a c-axis oriented Pb.sub.5 Ge.sub.3 O.sub.11 FE layer and an upper electrode; wherein the FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and source, drain and gate electrodes.

Abstract: A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces.

Abstract: A method is provided for forming intermediate levels in an integrated circuit dielectric during a damascene process using a hard mask layer to transfer the pattern of a photoresist mask having at least one intermediate thickness. The dielectric is covered with a hard mask layer, and the hard mask layer is covered with the photoresist mask. The photoresist mask pattern is transferred into the hard mask pattern so that the hard mask pattern has at least one intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the hard mask pattern. The hard mask pattern is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is etched to a second depth, less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias.

Abstract: A dynamic random access memory device having a ferroelectric thin film perovskite (Ba.sub.1-x Sr.sub.x)TiO.sub.3 layer sandwiched by top and bottom (Ba.sub.1-x Sr.sub.x)RuO.sub.3 electrodes. The memory device is made by a MOCVD process including the steps of providing a semiconductor substrate, heating the substrate, exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2, thereafter exposing the substrate to precursors including at least TiO(C.sub.2 H.sub.5).sub.4 and thereafter exposing the substrate to precursors including at least Ru (C.sub.5 H.sub.5).sub.2.

Abstract: A dynamic random access memory device having a ferroelectric thin film perovskite (Ba.sub.1-x Sr.sub.x)TiO.sub.3 layer sandwiched by top and bottom (Ba.sub.1-x Sr.sub.x)RuO.sub.3 electrodes. The memory device is made by a MOCVD process including the steps of providing a semiconductor substrate, heating the substrate, exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2, thereafter exposing the substrate to precursors including at least TiO(C.sub.2 H.sub.5).sub.4 and thereafter exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2.

Abstract: A ferroelectric memory device having a perovskite thin film of a rare earth manganate and processes for manufacturing the same. The perovskite thin film layer has properties consistent with high quality nonvolatile memory devices. The perovskite thin film layer can be applied by a MOCVD process, by a MOD process, or a liquid source delivery process, all of which are described.

Abstract: The chemical vapor deposition of hydridospherosiloxane to generate films of SiO.sub.2 at low temperatures on substrates that cannot withstand high temperatures. The chemical vapor deposition process synthesized compounds with the general formula,(HSiO.sub.3/2).sub.n,with n being an even number ranging from 8 to a very large number. More particularly, it relates to the vapor deposition of oligomeric hydrogensilsesquioxanes, henceforth referred to as hydridospherosiloxanes. The hydridospherosiloxanes are used directly in a chemical vapor deposition reactor to generate films of SiO.sub.2 at low temperatures on substrates that cannot withstand high temperatures. Hydridospherosiloxanes and soluble hydrogensilsesquioxane resin are produced having the formula(HSiO.sub.3/2).sub.n,where n is an even integer greater than 8.

Abstract: A method to produce high quality doped and undoped lead zirconate titanate (PZT) thin films by metalorganic chemical vapor deposition is disclosed. The PZT thin films with the perovskite structure were deposited on sapphire disks, Pt/Ti/SiO.sub.2 /Si wafers, and RuO.sub.x /SiO.sub.2 /Si wafers by both hot-wall and cold-wall CVD reactors at deposition temperature as low as 550.degree. C. and a reduced pressure 6 torr. The source materials include metalorganic precursors and oxidizing agent. The metalorganic precursors can be metal alkoxides, metal acetylacetonates, or metal .beta.-diketonates. Preferably, the precursors are lead tetramethylheptadione for Pb component, zirconium tetramethylheptadione for Zr component, and titanium ethoxide for Ti component and the oxidizing agent is oxygen. The stoichiometry of the films can be easily controlled by varying the individual precursor temperature and/or the flow rate of the carrier gas. The Pb(Zr.sub.0.82 Ti.sub.0.18)O.sub.

Abstract: Metal organic chemical vapor deposition (MOCVD) is used to form a layer of a metal oxide on the surfaces and within the pores of a porous ceramic material. The metal oxide is formed from one or more inexpensive metal organic precursors which permeate the pores of the substrate as a vapor. Surface reactions on the heated substrate convert the metal organic precursors to their metal oxide. The technique has particular utility in creating catalysts with very large surface areas and in providing a protective coating on ceramic materials that prevents or reduces damage from hostile environments. In a preferred embodiment, aluminum isopropoxide, [(CH.sub.3).sub.2 CHO].sub.3 Al, and titanium ethoxide, Ti(C.sub.2 H.sub.5 O).sub.4, are used simultaneously or successively as precursors to generate a Al.sub.2 TiO.sub.5 coating on a porous ceramic substrate such as SiC or porous refractory cement candle filters.