Patents by Inventor Chien-Hsuan CHANG

Chien-Hsuan CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145389
    Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.
    Type: Application
    Filed: July 28, 2023
    Publication date: May 2, 2024
    Inventors: Li-Chiu WENG, Yew Teck TIEO, Ming-Hsuan WANG, Chia-Cheng CHEN, Wei-Yi CHANG, Jen-Hang YANG, Chien-Hsiung HSU
  • Publication number: 20240137165
    Abstract: A computing device includes: a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time; a first computing circuit, for computing a payload time according to a packet length and a packet rate; a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 25, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chien-Hsun Liao, Wei-Hsuan Chang
  • Publication number: 20240121685
    Abstract: A method of reducing gray energy consumption and achieving optimal gray energy saving for carbon neutralization is proposed. In a cellular network, each cell or BS (group of cells) has renewable (green) and non-renewable (gray, on-grid power) energy sources. The renewable (green) energy is highly variable and unpredictable, while non-renewable (gray, on-grid power) is stable but is not renewable and thus has more carbon impact. Each cell or BS (group of cells) services is associated UEs when it is on. In one novel aspect, a cell or BS (group of cells) that consumes more non-renewable energy can give some or all of its served UEs to another cell or BS (group of cells) that consumes less non-renewable energy.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 11, 2024
    Inventors: Chien-Sheng Yang, I-Kang Fu, YUAN-CHIEH LIN, Chia-Lin Lai, Yu-Hsin Lin, Yun-Hsuan Chang
  • Patent number: 11817782
    Abstract: An inverter device includes a converter circuit and a filter. The converter circuit converts a DC input voltage into an AC intermediate voltage based on six control signals, and includes first and second converters. Each of the first and second converters includes three switches, two diodes and a coupled inductor circuit. The switches of the first converter operate respectively based on three of the control signals. The switches of the second converter operate respectively based on the other three of the control signals. The filter filters the AC intermediate voltage to generate an AC output voltage.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: November 14, 2023
    Assignee: I SHOU UNIVERSITY
    Inventors: Chien-Hsuan Chang, Yi-Fan Chen
  • Publication number: 20230068053
    Abstract: An inverter device includes a converter circuit and a filter. The converter circuit converts a DC input voltage into an AC intermediate voltage based on six control signals, and includes first and second converters. Each of the first and second converters includes three switches, two diodes and a coupled inductor circuit. The switches of the first converter operate respectively based on three of the control signals. The switches of the second converter operate respectively based on the other three of the control signals. The filter filters the AC intermediate voltage to generate an AC output voltage.
    Type: Application
    Filed: January 6, 2022
    Publication date: March 2, 2023
    Inventors: Chien-Hsuan CHANG, Yi-Fan CHEN
  • Patent number: 11205969
    Abstract: An inverter device includes a converter circuit and an output circuit. The converter circuit generates a DC intermediate voltage based on a DC input voltage from a power source. The converter circuit includes: a first inductor and a first switch that are coupled in series across the power source; a second switch and a second inductor that are coupled in series across the power source; and a diode and a capacitor that are coupled in series between a common node of the first inductor and the first switch and a common node of the second switch and the second inductor. The output circuit generates an AC output voltage based on the DC intermediate voltage across the capacitor.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: December 21, 2021
    Assignee: I SHOU UNIVERSITY
    Inventor: Chien-Hsuan Chang
  • Publication number: 20210305912
    Abstract: An inverter device includes a converter circuit and an output circuit. The converter circuit generates a DC intermediate voltage based on a DC input voltage from a power source. The converter circuit includes: a first inductor and a first switch that are coupled in series across the power source; a second switch and a second inductor that are coupled in series across the power source; and a diode and a capacitor that are coupled in series between a common node of the first inductor and the first switch and a common node of the second switch and the second inductor. The output circuit generates an AC output voltage based on the DC intermediate voltage across the capacitor.
    Type: Application
    Filed: August 18, 2020
    Publication date: September 30, 2021
    Inventor: Chien-Hsuan CHANG