Patents by Inventor Chien-Hsuan Liu
Chien-Hsuan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955865Abstract: A three-axis voice coil motor including a base, a spherical bearing, a magnetic component, an X-coil group, a Y-coil group, and at least one Z-coil group is provided. The base has a supporting pole. The spherical bearing is rotatably sleeved around the supporting pole. The magnetic component is securely sleeved around the spherical bearing and the magnetic component rotates along with the spherical bearing. The X-coil group is disposed around the magnetic component along an X-axial direction passing through the spherical bearing, and the X-coil group has first gaps. The Y-coil group is disposed around the magnetic component along a Y-axial direction passing through the spherical bearing, and the Y-coil group has second gaps. The Z-coil group is disposed around the magnetic component along a Z-axial direction passing through the spherical bearing.Type: GrantFiled: October 19, 2021Date of Patent: April 9, 2024Assignee: National Cheng-Kung UniversityInventors: Chien-Sheng Liu, Yi-Hsuan Lin, Chiu-Nung Yeh
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Patent number: 11925017Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.Type: GrantFiled: January 13, 2020Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Publication number: 20230260933Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.Type: ApplicationFiled: April 25, 2023Publication date: August 17, 2023Inventor: Chien-Hsuan LIU
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Patent number: 11670604Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.Type: GrantFiled: August 16, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chien-Hsuan Liu
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Publication number: 20210375796Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Inventor: Chien-Hsuan LIU
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Patent number: 11121141Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: GrantFiled: May 6, 2019Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Patent number: 11094650Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.Type: GrantFiled: February 11, 2020Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventor: Chien-Hsuan Liu
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Publication number: 20210249365Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventor: Chien-Hsuan LIU
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Publication number: 20200152648Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Patent number: 10535670Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.Type: GrantFiled: February 25, 2016Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Publication number: 20190259771Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Patent number: 10283510Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: GrantFiled: September 18, 2017Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Patent number: 9966302Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.Type: GrantFiled: February 3, 2017Date of Patent: May 8, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chien-Hsuan Liu
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Publication number: 20180006046Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Patent number: 9768182Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: GrantFiled: May 18, 2016Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Publication number: 20170250188Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.Type: ApplicationFiled: February 25, 2016Publication date: August 31, 2017Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Publication number: 20170148666Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Inventor: CHIEN-HSUAN LIU
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Publication number: 20170110466Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: ApplicationFiled: May 18, 2016Publication date: April 20, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiang-Ming CHUANG, Chien-Hsuan LIU, Chih-Ming LEE, Kun-Tsang CHUANG, Hung-Che LIAO, Hsin-Chi CHEN
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Patent number: 9599888Abstract: Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.Type: GrantFiled: February 3, 2016Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsuan Liu, Jen-Pan Wang
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Patent number: 9595492Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.Type: GrantFiled: March 16, 2015Date of Patent: March 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chien-Hsuan Liu