Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin structure having a first fin portion and a second fin portion, forming a first dielectric layer on the substrate and on sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.