Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a first switch unit (201), a second switch unit (202), a third switch unit (203), a fourth switch unit (204), and a fifth switch unit (205). A signal input terminal of each shift register unit is coupled to an output terminal of a rear-stage shift register unit. A first clock input terminal receives a first clock signal to turn on/off the first and second switch units. The third switch unit receives a second clock signal. The fourth switch unit pulls up the output voltage of the output terminal according to a controlling signal from the first switch unit. The fifth switch unit pulls down the output voltage of the output terminal according to controlling signals from the second and third switch units.

Abstract: A shift register includes first and second shift register units. Two adjacent first shift register units respectively receive a first and second clock signal. Two adjacent second shift register units respectively receive a third and a fourth clock signal. Each first and second shift register unit includes a cascade data input terminal, a cascade data output terminal, an output terminal used to output a shift signal, a feedback terminal, and a reset terminal. The shift signals of the Mth second and Nth first shift register unit are respectively fed back to the feedback terminal of the (N+1)th first and Mth second shift register unit. The reset terminal and the cascade data output terminal of the Nth first and Mth second shift register unit are respectively connected to the output terminal and the cascade data input terminal of (N+1)th first and (M+1)th second shift register unit.

Abstract: A shift register includes individually connected shift register units. Each shift register unit includes a switching unit, a pre-charging unit, a pulse signal output unit, a low level voltage signal control unit, a first clock pulse signal input, a second clock pulse signal input, and an output. The first and the second clock pulse signal inputs respectively receive a first clock signal and a second clock signal, the first clock signal and the second clock signal having reverse clock pulses during each clock cycle. The switching unit receives at least one external starting signal and a high level signal, when the at least one external starting signal is high level, the switching unit is turned on and outputs the high level signal to the pre-charging unit. When the second clock signal is high level, the pre-charging unit receives the high level signal and charges, and when the first clock signal is high level, the pre-charging unit discharges.

Abstract: An active device array substrate includes a plurality of pixel units, a plurality of scan lines, a plurality of data lines. Each of the pixel units has an active device. The pixel units are arranged to form at least one group of a first pixel unit column and a second pixel unit column adjacent to each other, and the pixel units in the first pixel unit column and the second pixel unit column are vertically arranged. The scan lines and the data lines electrically connected to the corresponding active devices of the pixel units. Herein, the data line connected to the active devices of the pixel units of the first pixel unit column and the data line connected to the active devices of the pixel units of the second pixel unit column form a closed loop.

Abstract: A gate line driving module used on a liquid crystal display uses clock signal sources in replacement of a high level gate power source, such that the phenomenon of device characteristic drift occurring in the foregoing related art is avoided. The gate line driving module includes a plurality of odd-pixel gate line driving circuits, a plurality of even-pixel gate line driving circuits, and an auxiliary gate line driving circuit. A pair of neighboring odd-pixel gate line driving circuit and even-pixel gate line driving circuit exchange output signals thereof with each other in a forward or feedback manner for ensuring that each the odd-pixel gate line driving circuit and each the even-pixel gate line driving circuit are driven once. The auxiliary gate line driving circuit is used for ensuring that signal iteration of the gate line driving module is under normal operation.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a reverse clock signal input terminal (TSB), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a common node (P), a first switch circuit (31) providing a high level signal to the common node, a second switch circuit (32) providing a low level signal to the common node, a third switch circuit (33) providing a clock signal to the output terminal, a fourth switch circuit (34) providing a low level signal to the output terminal, and an inverter (36) connected between the output terminal and the reverse output terminal.

Abstract: A shift register of the present disclosure switches on and off various transistors in order to reduce power consumption. A high input voltage source and a low input voltage source of the shift register are spaced apart from each other so as to reduce signal noise distortion between the voltage sources. The shift register may be employed in a liquid crystal display (LCD).

Abstract: An exemplary shift register includes a plurality of shift register units, each of which includes an output circuit, an input circuit, and a logic circuit. The output circuit includes a clock transistor, a voltage stabilizing transistor, and an input circuit for receiving signals output by a previous shift register unit. The logic circuit receives signals output by the input circuit. When the input circuit outputs signals to switch on the clock transistor, the logic circuit outputs a low level voltage signal to shut off the voltage stabilizing transistor. Thus, the output circuit outputs signals via the clock circuit. On the other hand, when the input circuit outputs signals to shut off the clock transistor, the logic circuit outputs a high level voltage signal to turn on the voltage stabilizing transistor, so as to maintain the output circuit to output low level voltage signal.

Abstract: The present invention relates to a shift register and a liquid crystal display using the same. The liquid crystal display includes a liquid crystal panel, a data driving circuit and a scanning driving circuit. The data driving circuit and the scanning driving circuit each include a shift register. The shift register includes a plurality of shift register units. Two adjacent shift register units respectively receive two inverse clock signals and a VGL signal. Each shift register unit includes a signal output circuit, a signal input circuit, a first logic converting circuit, and a second logic converting circuit. The present shift register and a liquid crystal display have simple structure.

Abstract: A shift register of the present disclosure comprises a plurality of shift register units using alternating clock signals to shift signals. The shift register outputs signals having substantially no overlap with adjacent signals. The shift register may be employed in a liquid crystal display.

Abstract: A shift register of the present disclosure switches on and off various transistors in order to reduce power consumption. A high input voltage source and a low input voltage source of the shift register are spaced apart from each other so as to reduce signal noise distortion between the voltage sources. The shift register may be employed in a liquid crystal display (LCD).

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an input terminal (VIN), a first output terminal (VOUT1), a second output terminal (VOUT2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a nor gate, an inverter, and an and gate.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a first inverter (37) connected between the first common node and the second common node, and a second inverter (39) connected between the output terminal and the reverse output terminal.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a first switch unit (201), a second switch unit (202), a third switch unit (203), a fourth switch unit (204), and a fifth switch unit (205). A signal input terminal of each shift register unit is coupled to an output terminal of a rear-stage shift register unit. A first clock input terminal receives a first clock signal to turn on/off the first and second switch units. The third switch unit receives a second clock signal. The fourth switch unit pulls up the output voltage of the output terminal according to a controlling signal from the first switch unit. The fifth switch unit pulls down the output voltage of the output terminal according to controlling signals from the second and third switch units.

Abstract: An exemplary clock-pulse generator (60) includes an input port (63), an output port (64), a logic gate (601) having two inputs (602 and 603) and an output (604), an odd number of inverters (606) connected in series between the input port and one of the inputs of the logic gate, an even number of inverters (607 and 608) connected in series between the input port and the other input of the logic gate, and an inverter (605) connected between the output of the logic gate and the output port. The present invention also provides a shift register (6) using the clock-pulse generator.