Patents by Inventor Chien-Hsueh Shih
Chien-Hsueh Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8785321Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.Type: GrantFiled: September 30, 2011Date of Patent: July 22, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Chu Ko, Ming-Hsing Tsai, Chien-Hsueh Shih
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Patent number: 8623760Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.Type: GrantFiled: April 5, 2012Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Chen-Hua Yu, Ming-Shih Yeh
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Patent number: 8349730Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.Type: GrantFiled: June 25, 2010Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Shau-Lin Shue
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Publication number: 20120190191Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Applicant: Taiwan Semiconductor Manufaturing Company, Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Chen-Hua Yu, Ming-Shih Yeh
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Patent number: 8193087Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.Type: GrantFiled: November 28, 2006Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Chen-Hua Yu, Ming-Shih Yeh
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Publication number: 20120021602Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.Type: ApplicationFiled: September 30, 2011Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ting-Chu Ko, Ming-Hsing Tsai, Chien-Hsueh Shih
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Patent number: 8053892Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.Type: GrantFiled: January 27, 2006Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Chu Ko, Ming-Hsing Tsai, Chien-Hsueh Shih
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Publication number: 20100267232Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.Type: ApplicationFiled: June 25, 2010Publication date: October 21, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Shau-Lin Shue
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Patent number: 7777344Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.Type: GrantFiled: April 11, 2007Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Shau-Lin Shue
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Patent number: 7771579Abstract: A chemical solution for an electro chemical plating process includes an electro chemical plating solution; and an additive, added in the electro chemical plating solution, substantially consisting of a polymer with one or more kinds of impurities, wherein each kind of the impurities has a density, with respect to the polymer, lower then 1019 atoms/cc.Type: GrantFiled: December 3, 2004Date of Patent: August 10, 2010Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: Ting-Chu Ko, Chien-Hsueh Shih, Minghsing Tsai
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Patent number: 7582557Abstract: An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition.Type: GrantFiled: January 13, 2006Date of Patent: September 1, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsueh Shih, Chen Hua Yu
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Patent number: 7538434Abstract: A conductive polymer between two metallic layers acts a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.Type: GrantFiled: March 8, 2005Date of Patent: May 26, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Hung-Wen Su, Shau-Lin Shue
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Publication number: 20090117731Abstract: A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Shau-Lin Shue, Chien-Hsueh Shih, Ming-Shih Yeh, Ming-Han Lee
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Patent number: 7476306Abstract: Apparatus and method for metal electroplating. The apparatus for metal electroplating includes an electroplating tank for containing an electrolyte at a first temperature, a substrate holder for holding a semiconductor substrate, and a heater for heating the portion of the electrolyte adjacent to the substrate holder to a second temperature higher than the first temperature.Type: GrantFiled: April 1, 2004Date of Patent: January 13, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Wen Su, Chien-Hsueh Shih, Ming-Hsing Tsai
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Publication number: 20090004851Abstract: A selective electroless plating operation provides for the selective deposition of a metal film only on exposed silicon surfaces of a semiconductor substrate and not on other surfaces such as dielectric surfaces. The plating solution includes metal ions and advantageously also includes dopant impurity ions. The pure metal or metal alloy film formed on the exposed silicon surfaces is then heat treated to form a metal silicide on the exposed silicon surfaces and to drive the dopant impurities to the interface formed between the exposed silicon surfaces and the metal silicide film.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shau-Lin Shue, Ting-Chu Ko, Chien-Hsueh Shih
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Patent number: 7446034Abstract: An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition.Type: GrantFiled: June 27, 2006Date of Patent: November 4, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsueh Shih, Chen Hua Yu
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Publication number: 20080251919Abstract: A method for fabricating a semiconductor interconnect device. A preferred embodiment comprises forming a low-k or very low-k dielectric layer on a wafer substrate and forming a recess in the dielectric layer that exposes a region on the substrate to which electrical contact is desired. A barrier layer is formed by first forming an organic layer on the walls of the substrate, then forming a catalyst metal layer on the organic layer, and finally forming a barrier metal layer over the catalyst layer. The remainder of the recess formed in the dielectric layer is then filled with a conductive material such as copper that will function as the main electrical connector to the contact region on the substrate.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Inventors: Chien-Hsueh Shih, Shau-Lin Shue
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Publication number: 20080251922Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Inventors: Chien-Hsueh Shih, Shau-Lin Shue
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Patent number: 7413976Abstract: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.Type: GrantFiled: February 1, 2005Date of Patent: August 19, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Hung-Wen Su, Minghsing Tsai
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Patent number: 7332435Abstract: A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.Type: GrantFiled: March 4, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Shih-Wei Chou, Hung-Wen Su, Minghsing Tsai