Abstract: A rotor structure comprises core laminations, two ring covers, and a hollow shaft. The core laminations have a horizontal side with multiple equally angled lightening holes. Each ring cover has a horizontal inner surface that contacts the outermost horizontal side of the core lamination. The horizontal inner surface of the ring covers features guiding protrusions corresponding to the lightening holes. The guiding protrusions form grooves at their end surfaces that serve as oil inlets and outlets located along the inner and outer circumferential surfaces of the ring covers, respectively. The core laminations and the ring covers are mounted on the hollow shaft, and the oil inlet of the ring cover is fluidly connected to the oil injection hole of the hollow shaft. The guiding protrusions can slow down the flow velocity centrifugally to ensure the consistency of the oil inlet and outlet.

Abstract: The present disclosure pertains to a motor stator cooling structure comprising a stator core and two oil spray rings attached to both ends of the stator core, respectively. The stator core comprises a yoke and multiple core teeth extending inward from the yoke. Each of the core teeth internally forms a cooling fluid channel extending axially along the stator core. Each oil spray ring is designed with staggered oil outlet holes and oil guide grooves. The staggered arrangement of the two oil spray rings causes the oil outlet holes at both ends of the stator core to interlace. It allows the cooling fluid to enter the stator core from both ends simultaneously and in a staggered manner along the axial direction, achieving a uniform cooling effect and ameliorating localized high-temperature conditions in the motor stator.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: A connector and a chamber are provided. The connector of the chamber includes the first sub connector, the second sub connector and the plurality of foldable connectors. Each wire can be covered by the connector and does not need to be exposed. The wire is protected and organized, and the appearance of the chamber is aesthetically pleasing. Moreover, when the chamber is in the close operation, the protrusion of each sub connector is disposed in the slide track of the former sub connector, and each sub connector is received in the accommodation space of the former sub connector, so that the requirement space of the connector is reduced and the volume of the chamber is reduced.

Abstract: A battery charging chamber is provided. The battery charging chamber charges or discharges a battery. The battery charging chamber includes a box, a cover and a connector. The box includes a first casing and a chassis. The chassis is disposed in a first accommodation space of the first casing for receiving the battery. The cover includes a second casing, a first plate, a second plate and an AC/DC conversion module. The first plate, the second plate and the AC/DC conversion module are disposed in a second accommodation space of the second casing. The first plate is made of metal and disposed between the second plate and a bottom of the second casing. The second plate includes a set of heat dissipation holes. The AC/DC conversion module is disposed between the second plate and the first plate. The box and the cover are pivotally connected with each other through the connector.

Abstract: A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.

Abstract: A system for separation of gas and solid at least comprises a cyclone trapping device and a negative pressure waste gas treatment device. The cyclone trapping device has a gas inlet and outlet chamber and a cyclone separation chamber communicating with each other, and the gas inlet and outlet chamber has a gas inlet tube communicating with a process waste gas source and a gas outlet tube communicating with the negative pressure waste gas treatment device. A process waste gas generated by the process waste gas source is introduced into the gas inlet and outlet chamber through the gas inlet tube to generate cyclones, thereby separating a portion of solid particles from the process waste gas, and transmitting the process waste gas to the negative pressure waste gas treatment device through the gas outlet tube in order to further separate the remaining solid particles from the process waste gas.

Abstract: A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.

Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

Abstract: The present invention provides a quick coupling probe card, utilized to test circuit board. The quick coupling probe card comprises a base, a coaxial connector, mechanical connector, and probe holding part, wherein the base has a first surface and a second surface corresponding to the first surface, the coaxial connector arranged on the base has one end above the first surface, and is coupled to the test machine for transmitting the high frequency signal, the mechanical connector is arranged on the first surface for coupling to the test machine, and is closer to a center of the base than the coaxial connector, and the probe holding part, arranged on the second surface and utilized to couple to the coaxial connector, has one end connected to a high frequency probe corresponding to one specific kind of the different kinds of pitches.

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

Abstract: A method for adjusting position of probing base comprises steps of providing a probing machine comprising a probing holder, a first probing base having a first probing needle comprising a plurality of first probing bodies wherein two adjacent tips of the first probing bodies h a first pitch, and a second probing base having a second probe comprising a plurality of second probing bodies in which two adjacent tips of the second probing bodies has a second pitch, thereafter, grabbing the first probing base and connecting the first probing base to the probing holder, acquiring first image with respect to the plurality of first probing bodies through visual identification module, and finally, adjusting roll angle of probing tips of the plurality of first needle bodies according to the first image. Alternatively, the present invention further provides a probing machine using the method for testing DUTs having different pitches.

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

Abstract: Disclosed are a laser-treated anti-deposition object with a main structure and a fluorine coating layer and a manufacturing method of the same. The fluorine coating layer covers a laser-treated surface of the main structure to form an anti-deposition surface, an initial surface of the main structure is subjected to a laser surface treatment step by a laser to become the laser-treated surface with a plurality of microstructures. The anti-deposition object contacts with a manufacturing process substance used or discharged during a manufacturing process performed by a manufacturing process equipment in a vacuum environment, and the anti-deposition surface of the object has a relatively high contact angle.

Abstract: Disclosed is an anti-deposition object for use in a vacuum environment with a main structure and a fluorine coating layer, the fluorine coating layer covers at least one surface of the main structure, the anti-deposition object contacts with a manufacturing process substance used or discharged during a manufacturing process performed by a manufacturing process equipment in the vacuum environment, the fluorine coating layer has a water droplet contact angle with the manufacturing process substance higher than that of the surface of the main structure, the fluorine coating layer has a hardness similar to or higher than that of the surface of the main structure, and the fluorine coating layer has a roughness lower than that of the surface of the main structure.

Abstract: Disclosed is an anti-deposition object with a main structure and a fluorine coating layer, the fluorine coating layer covers at least one surface of the main structure, the anti-deposition object contacts with a substance in an environment, the fluorine coating layer has a water droplet contact angle with the substance higher than that of the surface of the main structure, the fluorine coating layer has a hardness similar to or higher than that of the surface of the main structure, and the fluorine coating layer has a roughness lower than that of the surface of the main structure.

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.