Abstract: A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure has a base layer, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner over the base layer. The method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers, and the base layer. The method further includes partially or completely removing the base layer to form a recess, forming a protective structure in the recess, and forming an epitaxial structure filling the opening. In addition, the method includes partially removing the substrate from a backside surface of the substrate to form a contact opening exposing the protective structure and extending towards the epitaxial structure. The method includes forming a backside conductive contact in the contact opening.

Abstract: In an embodiment, a method includes: forming a first opening in a semiconductor substrate, in a plan view the first opening having a ring shape; forming a dielectric guard ring in the first opening; forming an active device along a first surface of the semiconductor substrate; forming first metallization layers over the active device; forming a second opening through the semiconductor substrate, the second opening adjacent to the ring shape of the dielectric guard ring; forming a conductive through via in the second opening; and forming second metallization layers over the first metallization layers.

Abstract: A power sequence monitoring system is disclosed, and comprises: a microprocessor and a control module. The microprocessor comprises a first conversion unit and a second conversion unit. The first conversion unit is used for converting a power-on signal received from a power management chip to a first digital signal, and the second conversion unit is adopted for converting a power-off signal received form the power management chip to a second digital signal. After receiving the first digital signal and the second digital signal from the microprocessor, and the control module outputs a plurality of power monitoring data to an electronic device, such that a user easily knows the power signal state of the host computer by the system of the present invention.

Abstract: A system for visualizing power signal sequence is disclosed, and comprises: a microprocessor and a control module. The microprocessor comprises a first conversion unit and a second conversion unit. The first conversion unit is used for converting a power-on signal received from a power management chip to a first digital signal, and the second conversion unit is adopted for converting a power-off signal received form the power management chip to a second digital signal. After receiving the first digital signal and the second digital signal from the microprocessor, and the control module outputs a plurality of power monitoring data to an electronic device, such that a user easily knows the power signal state of the host computer by the system of the present invention.

Abstract: A method for use in the manufacture of a microelectronic apparatus, the method comprising exposing a dummy field on a substrate by utilizing a lithographic scanner at a first speed, and exposing a production field on the substrate by utilizing the lithographic scanner at a second speed, where the first speed is substantially greater than the second speed. In a related embodiment, a method for use in the manufacture a microelectronic apparatus comprises exposing a non-critical layer of the apparatus by utilizing a lithographic scanner at a first speed, and exposing a critical layer of the apparatus by utilizing the lithographic scanner at a second speed, where the first speed is substantially greater than the second speed.

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract: System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner including a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method includes providing a water tank that connects to at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level.

Abstract: System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner comprising a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method comprises providing a water tank at at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level.

Abstract: System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner including a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method includes providing a water tank that connects to at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level.

Abstract: A method for processing substrates to manufacture semiconductor structures thereon includes analyzing at least one first processing parameter of a first apparatus for processing a substrate, thereby yielding at least one first throughput rate of the first apparatus. At least one second processing parameter of a second apparatus is analyzed for processing the substrate, thereby yielding at least one second throughput rate of the second apparatus. The first throughput rate and the second throughput rate are compared, thereby yielding at least one comparison result for processing the substrate.

Abstract: A method for improving critical dimension of a substrate is provided. Manufacturing data of a plurality of critical dimension deviations corresponding to a plurality of areas on the substrate is collected. A plurality of sensitivity data corresponding to the plurality of areas is also collected. A plurality of exposure dosage offsets corresponding to the plurality of areas are calculated based on the plurality of critical dimension deviations and the plurality of sensitivity data.

Abstract: A method for use in the manufacture of a microelectronic apparatus, the method comprising exposing a dummy field on a substrate by utilizing a lithographic scanner at a first speed, and exposing a production field on the substrate by utilizing the lithographic scanner at a second speed, where the first speed is substantially greater than the second speed. In a related embodiment, a method for use in the manufacture a microelectronic apparatus comprises exposing a non-critical layer of the apparatus by utilizing a lithographic scanner at a first speed, and exposing a critical layer of the apparatus by utilizing the lithographic scanner at a second speed, where the first speed is substantially greater than the second speed.

Abstract: A method for improving critical dimension of a substrate is provided. Manufacturing data of a plurality of critical dimension deviations corresponding to a plurality of areas on the substrate is collected. A plurality of sensitivity data corresponding to the plurality of areas is also collected. A plurality of exposure dosage offsets corresponding to the plurality of areas are calculated based on the plurality of critical dimension deviations and the plurality of sensitivity data.

Abstract: System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner comprising a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method comprises providing a water tank at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level.

Abstract: A method for processing substrates to manufacture semiconductor structures thereon includes analyzing at least one first processing parameter of a first apparatus for processing a substrate, thereby yielding at least one first throughput rate of the first apparatus. At least one second processing parameter of a second apparatus is analyzed for processing the substrate, thereby yielding at least one second throughput rate of the second apparatus. The first throughput rate and the second throughput rate are compared, thereby yielding at least one comparison result for processing the substrate.

Abstract: A method and apparatus for scanning electron microscope measurements which maintains a constant e-beam dose to the surface of a wafer being measured and thereby maintains a constant resist shrinkage. The apparatus provides a magnetic lens, a movable wafer holder to adjust the distance between a wafer and the magnetic lens, an image detector, means to determine the distance between the wafer and the magnetic lens, a retarding voltage applied to the wafer holder, means to adjust the retarding voltage, and means to focus the magnetic lens. The apparatus also provides feedback systems between the movable wafer holder and the means to determine the distance between the wafer and the magnetic lens, between the image detector and the means to adjust the retarding voltage, and between the image detector and means to focus the magnetic lens so these adjustments can be made automatically. The method first sets the distance between the wafer and the magnetic lens.

Abstract: Reducing photoresist shrinkage by plasma treatment is disclosed. A semiconductor wafer having one or more photoresist layers is plasma treated, such as plasma curing, plasma etching, and/or high-density plasma etching the wafer. After plasma treating, one or more critical dimensions on the photoresist layers is measured using an electron beam, such as by using a scanning electron microscope (SEM). The plasma treating of the wafer prior to measuring the critical dimensions using the electron beam decreases shrinkage of the photoresist layer when using the electron beam.