Patents by Inventor Chien-Hsun Lu
Chien-Hsun Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162833Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
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Publication number: 20240092662Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.Type: ApplicationFiled: February 9, 2023Publication date: March 21, 2024Inventors: Chien-Yen CHEN, Yi-Hsun HUANG, Pin-Yun LIN, Anggraeni Kumala DEWI, Koyeli DAS, Uttara SUKUL, Tsung-Hsien CHEN, Raju Kumar SHARMA, Cheng-Kang LU, Chung-Ming LU
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Publication number: 20240071656Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.Type: ApplicationFiled: January 13, 2023Publication date: February 29, 2024Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
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Patent number: 11785233Abstract: The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.Type: GrantFiled: December 14, 2020Date of Patent: October 10, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chieh Chan, Tai-Jung Wu, Ming-An Wu, Chien-Hsun Lu
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Patent number: 11659136Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.Type: GrantFiled: March 31, 2021Date of Patent: May 23, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Che-Wei Yeh, Chien-Hsun Lu, Zhan-Yao Gu, Chun-Chieh Chan
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Patent number: 11412302Abstract: A detection circuit and a wake-up method are provided. The detection circuit is adapted to a high definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed rate link (FRL) mode to detect whether or not an HDMI transmitter starts to transmit video packets through the FRL. The detection circuit includes a signal detection circuit detecting whether or not signal exists on the FRL and an FRL packet determination circuit determining whether or not the FRL packets are the video packets according to a variable value characteristic of the video packets and/or a fixed value characteristic of gap packets. An existence of the signal on the FRL indicates an existence of FRL packets on the FRL. When the FRL packets are the video packets, the FRL packet determination circuit wakes the HDMI receiver from the power-saving mode to resolve the video packets and display videos.Type: GrantFiled: July 5, 2021Date of Patent: August 9, 2022Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chun-Chieh Chan, Ming-An Wu, Chia-Hao Chang, Chien-Hsun Lu
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Publication number: 20220124282Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.Type: ApplicationFiled: March 31, 2021Publication date: April 21, 2022Inventors: CHE-WEI YEH, CHIEN-HSUN LU, ZHAN-YAO GU, CHUN-CHIEH CHAN
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Publication number: 20220109908Abstract: A detection circuit and a wake-up method are provided. The detection circuit is adapted to a high definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed rate link (FRL) mode to detect whether or not an HDMI transmitter starts to transmit video packets through the FRL. The detection circuit includes a signal detection circuit detecting whether or not signal exists on the FRL and an FRL packet determination circuit determining whether or not the FRL packets are the video packets according to a variable value characteristic of the video packets and/or a fixed value characteristic of gap packets. An existence of the signal on the FRL indicates an existence of FRL packets on the FRL. When the FRL packets are the video packets, the FRL packet determination circuit wakes the HDMI receiver from the power-saving mode to resolve the video packets and display videos.Type: ApplicationFiled: July 5, 2021Publication date: April 7, 2022Inventors: CHUN-CHIEH CHAN, MING-AN WU, CHIA-HAO CHANG, CHIEN-HSUN LU
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Patent number: 11137971Abstract: A data packing circuit and a data packing method operated in a high definition multimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided. The data packing circuit can output a plurality of FRL super blocks at a plurality of unit times. In the data packing method, multiple valid data inputted to the data packing circuit at the (i)th unit time are mapped to a plurality of FRL characters, and the FRL characters are stored to the first or the second buffer. At the same time, an amount of tri-byte of the multiple valid data is counted for determining number and positions for inserting gap characters to form the (i)th FRL super block, which is outputted at the (i+1)th unit time. The numeral āiā is a positive integer.Type: GrantFiled: October 29, 2020Date of Patent: October 5, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Ying-Ying Song, Chien-Hsun Lu, Yi-Han Peng, Chun-Chieh Chan
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Publication number: 20210208838Abstract: A data packing circuit and a data packing method operated in a high definition multimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided. The data packing circuit can output a plurality of FRL super blocks at a plurality of unit times. In the data packing method, multiple valid data inputted to the data packing circuit at the (i)th unit time are mapped to a plurality of FRL characters, and the FRL characters are stored to the first or the second buffer. At the same time, an amount of tri-byte of the multiple valid data is counted for determining number and positions for inserting gap characters to form the (i)th FRL super block, which is outputted at the (i+1)th unit time. The numeral āiā is a positive integer.Type: ApplicationFiled: October 29, 2020Publication date: July 8, 2021Inventors: YING-YING SONG, CHIEN-HSUN LU, YI-HAN PENG, CHUN-CHIEH CHAN
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Publication number: 20210185291Abstract: The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.Type: ApplicationFiled: December 14, 2020Publication date: June 17, 2021Inventors: CHUN-CHIEH CHAN, TAI-JUNG WU, MING-AN WU, CHIEN-HSUN LU
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Patent number: 9684620Abstract: A signal relaying circuit includes an input interface arranged for receiving an input signal; a DisplayPort (DP) output interface arranged for outputting a DP-like signal, where the input interface and the DP output interface correspond to different interface standards; and a relaying circuit coupled between the input interface and the DP output interface, arranged for relaying the input signal to the DP output interface according to the characteristics of channels, so as to generate the DP-like signal. A signal receiving circuit, signal relaying method and signal receiving method are also disclosed.Type: GrantFiled: August 26, 2014Date of Patent: June 20, 2017Assignee: Realtek Semiconductor Corp.Inventors: Chih-Yuan Yang, Shin-Yu Lin, Tzuo-Bo Lin, Chien-Hsun Lu
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Publication number: 20150067227Abstract: A signal relaying circuit includes an input interface arranged for receiving an input signal; a DisplayPort (DP) output interface arranged for outputting a DP-like signal, where the input interface and the DP output interface correspond to different interface standards; and a relaying circuit coupled between the input interface and the DP output interface, arranged for relaying the input signal to the DP output interface according to the characteristics of channels, so as to generate the DP-like signal. A signal receiving circuit, signal relaying method and signal receiving method are also disclosed.Type: ApplicationFiled: August 26, 2014Publication date: March 5, 2015Inventors: Chih-Yuan Yang, Shin-Yu Lin, Tzuo-Bo Lin, Chien-Hsun Lu
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Patent number: 7598840Abstract: A MOV includes a MOV body, a first lead, a thermal cut-off fuse, a second lead and a silver electrode area. The MOV of the present invention employs the silver electrode area formed on and electrically coupled to the MOV body, thus the MOV has a lower inductance, which accordingly, enables the MOV to have a high and sound thermal conductivity. Hence, the MOV can fleetly and perfectly transfer heat to the thermal cut-off fuse in case of over-voltages, thus enabling the thermal cut-off fuse to cut off the power more quickly.Type: GrantFiled: July 24, 2007Date of Patent: October 6, 2009Assignee: CeNtRa Science (holdings) LtdInventor: Chien-Hsun Lu
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Publication number: 20080088404Abstract: A MOV includes a MOV body, a first lead, a thermal cut-off fuse, a second lead and a silver electrode area. The MOV of the present invention employs the silver electrode area formed on and electrically coupled to the MOV body, thus the MOV has a lower inductance, which accordingly, enables the MOV to have a high and sound thermal conductivity. Hence, the MOV can fleetly and perfectly transfer heat to the thermal cut-off fuse in case of over-voltages, thus enabling the thermal cut-off fuse to cut off the power more quickly.Type: ApplicationFiled: July 24, 2007Publication date: April 17, 2008Applicant: CENTRA SCIENCE (HOLDINGS) LTD.Inventor: Chien-Hsun Lu