Abstract: A falling-edge modulation signal receiver is configured to process an input signal having a duty cycle varying with a bit value of the input signal. The receiver includes: a phase-locked loop for generating an oversampling clock according to the input signal which correlates with a signal clock, wherein the oversampling frequency is not lower than five times the frequency of the signal clock; an oversampling circuit for sampling the input signal according to the oversampling clock and thereby generating multiple groups of data which as a whole is corresponding to a single bit of the input signal; and a decision circuit for ascertaining that X bits of the multiple groups of data are 1 and determining the value of the single bit according to the X. When the X is greater/less than a threshold, the decision circuit determines that the value of the single bit is 1/0.

Abstract: An audio restore circuit includes an audio tracking circuit, a clock adjustment circuit, and an audio generator circuit. The audio tracking circuit is configured to generate a first control signal according to a sampling rate of an audio sampled signal and a clock rate of an audio clock signal. The clock adjustment circuit is configured to adjust the clock rate of the audio clock signal according to the first control signal. The audio generator circuit is configured to output a plurality of audio output signals according to the audio sampled signal and the audio clock signal.

Abstract: The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.

Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.

Abstract: A detection circuit and a wake-up method are provided. The detection circuit is adapted to a high definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed rate link (FRL) mode to detect whether or not an HDMI transmitter starts to transmit video packets through the FRL. The detection circuit includes a signal detection circuit detecting whether or not signal exists on the FRL and an FRL packet determination circuit determining whether or not the FRL packets are the video packets according to a variable value characteristic of the video packets and/or a fixed value characteristic of gap packets. An existence of the signal on the FRL indicates an existence of FRL packets on the FRL. When the FRL packets are the video packets, the FRL packet determination circuit wakes the HDMI receiver from the power-saving mode to resolve the video packets and display videos.

Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.

Abstract: A detection circuit and a wake-up method are provided. The detection circuit is adapted to a high definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed rate link (FRL) mode to detect whether or not an HDMI transmitter starts to transmit video packets through the FRL. The detection circuit includes a signal detection circuit detecting whether or not signal exists on the FRL and an FRL packet determination circuit determining whether or not the FRL packets are the video packets according to a variable value characteristic of the video packets and/or a fixed value characteristic of gap packets. An existence of the signal on the FRL indicates an existence of FRL packets on the FRL. When the FRL packets are the video packets, the FRL packet determination circuit wakes the HDMI receiver from the power-saving mode to resolve the video packets and display videos.

Abstract: A data packing circuit and a data packing method operated in a high definition multimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided. The data packing circuit can output a plurality of FRL super blocks at a plurality of unit times. In the data packing method, multiple valid data inputted to the data packing circuit at the (i)th unit time are mapped to a plurality of FRL characters, and the FRL characters are stored to the first or the second buffer. At the same time, an amount of tri-byte of the multiple valid data is counted for determining number and positions for inserting gap characters to form the (i)th FRL super block, which is outputted at the (i+1)th unit time. The numeral ‘i’ is a positive integer.

Abstract: A data packing circuit and a data packing method operated in a high definition multimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided. The data packing circuit can output a plurality of FRL super blocks at a plurality of unit times. In the data packing method, multiple valid data inputted to the data packing circuit at the (i)th unit time are mapped to a plurality of FRL characters, and the FRL characters are stored to the first or the second buffer. At the same time, an amount of tri-byte of the multiple valid data is counted for determining number and positions for inserting gap characters to form the (i)th FRL super block, which is outputted at the (i+1)th unit time. The numeral ‘i’ is a positive integer.

Abstract: The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.

Abstract: A signal relaying circuit includes an input interface arranged for receiving an input signal; a DisplayPort (DP) output interface arranged for outputting a DP-like signal, where the input interface and the DP output interface correspond to different interface standards; and a relaying circuit coupled between the input interface and the DP output interface, arranged for relaying the input signal to the DP output interface according to the characteristics of channels, so as to generate the DP-like signal. A signal receiving circuit, signal relaying method and signal receiving method are also disclosed.

Abstract: A signal relaying circuit includes an input interface arranged for receiving an input signal; a DisplayPort (DP) output interface arranged for outputting a DP-like signal, where the input interface and the DP output interface correspond to different interface standards; and a relaying circuit coupled between the input interface and the DP output interface, arranged for relaying the input signal to the DP output interface according to the characteristics of channels, so as to generate the DP-like signal. A signal receiving circuit, signal relaying method and signal receiving method are also disclosed.

Abstract: A MOV includes a MOV body, a first lead, a thermal cut-off fuse, a second lead and a silver electrode area. The MOV of the present invention employs the silver electrode area formed on and electrically coupled to the MOV body, thus the MOV has a lower inductance, which accordingly, enables the MOV to have a high and sound thermal conductivity. Hence, the MOV can fleetly and perfectly transfer heat to the thermal cut-off fuse in case of over-voltages, thus enabling the thermal cut-off fuse to cut off the power more quickly.

Abstract: A MOV includes a MOV body, a first lead, a thermal cut-off fuse, a second lead and a silver electrode area. The MOV of the present invention employs the silver electrode area formed on and electrically coupled to the MOV body, thus the MOV has a lower inductance, which accordingly, enables the MOV to have a high and sound thermal conductivity. Hence, the MOV can fleetly and perfectly transfer heat to the thermal cut-off fuse in case of over-voltages, thus enabling the thermal cut-off fuse to cut off the power more quickly.