Patents by Inventor Chien-Hua Cheng

Chien-Hua Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160378175
    Abstract: A power supply circuit comprises a power supply unit for powering components of the computing server, a power regulator connected to the power supply unit for regulating electric power supply to the components, and an activator connected to the power regulator for activating the power regulator. The power regulator is configured to initiate adjustment of an amount of electric power supplied from the power supply unit to the components after being activated by the activator.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 29, 2016
    Inventors: Chih-Wei Wu, Chien-Hua Cheng, Wei-Tien Chen, Samuel Fanchiang
  • Patent number: 9229484
    Abstract: An electronic apparatus includes a first assembly and a second assembly. The first assembly includes at least one hook and at least one elastic locating member. The second assembly includes at least one hook groove and at least one locating groove. The second assembly receives the hook of the first assembly by the hook groove along a first assembling direction. The second assembly makes the hook engaged to the hook groove along a second assembling direction. When the second assembly moves relative to the first assembly along the second assembling direction, the elastic locating member gets into the locating groove, thereby fastening the first assembly and the second assembly.
    Type: Grant
    Filed: June 22, 2014
    Date of Patent: January 5, 2016
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Pai-Feng Chen, Chao-Cheng Shao, Ming-Fu Chen, Tsung-Lin Yang, Chien-Hua Cheng, Chung-Kuo Lai
  • Publication number: 20150253812
    Abstract: An electronic apparatus includes a first assembly and a second assembly. The first assembly includes at least one hook and at least one elastic locating member. The second assembly includes at least one hook groove and at least one locating groove. The second assembly receives the hook of the first assembly by the hook groove along a first assembling direction. The second assembly makes the hook engaged to the hook groove along a second assembling direction. When the second assembly moves relative to the first assembly along the second assembling direction, the elastic locating member gets into the locating groove, thereby fastening the first assembly and the second assembly.
    Type: Application
    Filed: June 22, 2014
    Publication date: September 10, 2015
    Inventors: Pai-Feng CHEN, Chao-Cheng SHAO, Ming-Fu CHEN, Tsung-Lin YANG, Chien-Hua CHENG, Chung-Kuo LAI
  • Patent number: 8102291
    Abstract: A quantizer of a sigma-delta modulator includes a pulse width modulator (PWM), a converter and a voltage level tracing device. The PWM receives an input signal, and generates a PWM signal according to one or more sawtooth waves and one or more reference voltages. The converter is connected to the output of the PWM and digitizes the PWM signal to generate an output digital value. The voltage level tracing device is connected to the output of the converter, and receives the output digital value to generate a reference voltage adjustment value. The reference voltage adjustment value is transmitted to the PWM for adjusting the reference voltage, so as to change the next corresponding voltage level of the sawtooth wave to track the input signal.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: January 24, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien Hua Cheng, Tim Kuei Shia, Jia Chun Huang
  • Patent number: 7965124
    Abstract: A switched-capacitor (SC) circuit relating to summing and integration algorithms is provided. The SC circuit submitted by the present invention benefits from better closed-loop bandwidth performance because of combining positive and negative feedback loops of a high gain amplifier. In addition, the SC circuit submitted by the present invention not only provides differential output signal obtained by a summing (or integration) algorithm of input voltage signals and reference voltage signals and forward drives such differential output signal to a next stage SC circuit, but also provides flexible and accurate coefficient design for every individual input and reference voltage signals in the said algorithm. Besides, if the circuit manner of alternate resetting is disabled or removed, the SC summing circuit submitted by the present invention can serve as an SC integration circuit.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: June 21, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Tim Kuei Shia, Jia-Chun Huang, Chien-Hua Cheng, Bo-Wei Chen
  • Publication number: 20110122009
    Abstract: A quantizer of a sigma-delta modulator includes a pulse width modulator (PWM), a converter and a voltage level tracing device. The PWM receives an input signal, and generates a PWM signal according to one or more sawtooth waves and one or more reference voltages. The converter is connected to the output of the PWM and digitizes the PWM signal to generate an output digital value. The voltage level tracing device is connected to the output of the converter, and receives the output digital value to generate a reference voltage adjustment value. The reference voltage adjustment value is transmitted to the PWM for adjusting the reference voltage, so as to change the next corresponding voltage level of the sawtooth wave to track the input signal.
    Type: Application
    Filed: March 4, 2010
    Publication date: May 26, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien Hua CHENG, Tim Kuei Shia, Jia Chun Huang
  • Patent number: 7646583
    Abstract: A common centroid symmetric structure capacitor is provided, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is adjacent to the second metal layer, the third metal layer is adjacent to the first metal layer, the fourth metal layer is adjacent to the second metal layer, and the first metal layer is symmetric to the fourth metal layer, the second metal layer is symmetric to the third metal layer. Each of the metal layers has two sets of metal wires, each set has a plurality of metal wires, and each of the metal wires in each set is arranged in an interlaced manner.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: January 12, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Szu-Kang Hsien, I-Hsun Chen, Chien-Hua Cheng
  • Publication number: 20080158772
    Abstract: A common centroid symmetric structure capacitor is provided, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is adjacent to the second metal layer, the third metal layer is adjacent to the first metal layer, the fourth metal layer is adjacent to the second metal layer, and the first metal layer is symmetric to the fourth metal layer, the second metal layer is symmetric to the third metal layer. Each of the metal layers has two sets of metal wires, each set has a plurality of metal wires, and each of the metal wires in each set is arranged in an interlaced manner.
    Type: Application
    Filed: June 4, 2007
    Publication date: July 3, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Szu-Kang Hsien, I-Hsun Chen, Chien-Hua Cheng