Abstract: A method and system for DRAM refresh wherein the refresh rate is proportional to the current leakage of one or more sampling cells. The sampling cells selected are representative of the nominal leakage condition of the DRAM array and track the DRAM cell leakage rates, which are dependent upon manufacturing process variations, application influences, voltage variations and the temperature of the system, both locally and globally. As the current leakage through the DRAM increases, the refresh cycle repetition frequency increases and accordingly decreases for low leakage conditions. By adjusting the refresh rate in the manner described by the invention disclosed herein, the semiconductor conserves power by reducing unnecessary refresh cycles, generates the required delay between cycles without undue power consumption and provides a cost effective means that does not require external settings and calibration to optimize the refresh rate for the variations heretofore mentioned.

Abstract: A method and system for DRAM refresh wherein the refresh rate is proportional to the current leakage of one or more sampling cells. The sampling cells selected are representative of the nominal leakage condition of the DRAM array and track the DRAM cell leakage rates, which are dependent upon manufacturing process variations, application influences, voltage variations and the temperature of the system, both locally and globally. As the current leakage through the DRAM increases, the refresh cycle repetition frequency increases and accordingly decreases for low leakage conditions. By adjusting the refresh rate in the manner described by the invention disclosed herein, the semiconductor conserves power by reducing unnecessary refresh cycles, generates the required delay between cycles without undue power consumption and provides a cost effective means that does not require external settings and calibration to optimize the refresh rate for the variations heretofore mentioned.