Patents by Inventor Chien-Hua Tsai
Chien-Hua Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974302Abstract: A method and a User Equipment (UE) for beam operations are provided. The method includes monitoring at least one of a plurality of Control Resource Sets (CORESETs) configured for the UE within an active Bandwidth Part (BWP) of a serving cell in a time slot; and applying a first Quasi Co-Location (QCL) assumption of a first CORESET of a set of one or more of the monitored at least one of the plurality of CORESETs to receive a Downlink (DL) Reference Signal (RS), wherein the first CORESET is associated with a monitored search space configured with a lowest CORESET Identity (ID) among the set of one or more of the monitored at least one of the plurality of CORESETs.Type: GrantFiled: April 6, 2023Date of Patent: April 30, 2024Assignee: Hannibal IP LLCInventors: Chien-Chun Cheng, Tsung-Hua Tsai, Yu-Hsin Cheng, Wan-Chen Lin
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Patent number: 11923315Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.Type: GrantFiled: July 12, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
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Patent number: 11916282Abstract: An antenna apparatus includes a feeding antenna inside an electronic device and one or more antenna elements, such as a floating metal antenna, disposed on a rear cover of the electronic device. The floating metal antenna and a feeding antenna inside the electronic device may form a coupling antenna structure. The feeding antenna may be an antenna fastened on an antenna support (which may be referred to as a support antenna). The feeding antenna may alternatively be a slot antenna formed by slitting on a metal middle frame of the electronic device. The antenna apparatus may be implemented in limited design space, thereby effectively saving antenna design space inside the electronic device. The antenna apparatus may generate excitation of a plurality of resonance modes, so that antenna bandwidth and radiation characteristics can be improved.Type: GrantFiled: November 5, 2019Date of Patent: February 27, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Pengfei Wu, Chien-Ming Lee, Dong Yu, Chih Yu Tsai, Chih-Hua Chang, Arun Sowpati
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Patent number: 8673730Abstract: A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.Type: GrantFiled: November 21, 2011Date of Patent: March 18, 2014Assignee: Rexchip Electronics CorporationInventors: Pei-Chun Hung, Li-Hsun Chen, Chien-hua Tsai, Masahiko Ohuchi, Sheng-chang Liang
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Patent number: 8613861Abstract: A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.Type: GrantFiled: December 7, 2011Date of Patent: December 24, 2013Assignee: Rexchip Electronics CorporationInventors: Hsiao-chia Chen, Sheng-chang Liang, Chien-hua Tsai, Masahiko Ohuchi
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Patent number: 8546220Abstract: A method for fabricating buried bit lines comprises steps of: defining a plurality of parallel masked regions and a plurality of first etched regions each forming between any two neighboring masked regions on a surface of a substrate, and wherein the masked region is wider than the first etched region; etching the first etched regions to form a plurality of first trenches and a plurality of first pillars; forming two bit lines respectively on two sidewalls of each first trench; etching the first pillars to form a plurality of second pillars corresponding to the bit lines. The present invention uses a two-stage etching process to prevent pillars from bending or collapsing due to high aspect ratio. Moreover, the present invention has a simple process and is able to reduce cost and decrease cell size.Type: GrantFiled: July 18, 2012Date of Patent: October 1, 2013Assignee: Rexchip Electronics CorporationInventors: Isao Tanaka, Chien-hua Tsai
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Publication number: 20130237044Abstract: A method of manufacturing metal gates comprises the steps of: forming a plurality of parallel trenches on a substrate; forming sequentially a conductive layer and a protective layer on the surfaces of the substrate and trenches; removing the protective layer and conductive layer on the surface of the substrate and the protective layer on the bottom walls of the trenches through anisotropic etching to retain only the protective layer and conductive layer on the side walls; and finally removing the conductive layer not covered by the protective layer through isotropic etching to retain only the protective layer and conductive layer on the side walls so that two insulating gates are respectively formed on the side walls. Thus no isolation material is needed to be disposed at the bottom of the trenches, and the problem of excessive etching to the trenches that results in undesirable insulation can be averted.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Inventors: Hsiao-chia CHEN, Chien-hua TSAI
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Publication number: 20130146561Abstract: A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Inventors: Hsiao-chia Chen, Sheng-chang Liang, Chien-hua Tsai, Masahiko Ohuchi
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Publication number: 20130130463Abstract: A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.Type: ApplicationFiled: November 21, 2011Publication date: May 23, 2013Inventors: Pei-Chun HUNG, Li-Hsun CHEN, Chien-hua TSAI, Masahiko OHUCHI, Sheng-chang LIANG
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Patent number: 7598023Abstract: A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.Type: GrantFiled: September 28, 2005Date of Patent: October 6, 2009Assignee: United Microelectronics Corp.Inventors: Yi-Tyng Wu, Shih-Hung Chen, Huai-Hsuan Tsai, Chih-Hung Cheng, Chien-Hua Tsai, Hsuan-Hsu Chen
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Publication number: 20070093069Abstract: A purge process for a chip performed after a dry etching process is provided. The dry etching process is carried out inside a reaction chamber. The purge process is used to remove any byproducts produced by said dry etching process. The purge process includes injecting an inert gas into the reaction chamber to purge the same. Then, the gas inside the reaction chamber is exhausted. The purge process prevents the formation of defects in subsequent metal interconnect fabrication process.Type: ApplicationFiled: October 21, 2005Publication date: April 26, 2007Inventors: Chien-Hua Tsai, Yi-Chin Wu
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Publication number: 20070072130Abstract: A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.Type: ApplicationFiled: September 28, 2005Publication date: March 29, 2007Inventors: Yi-Tyng Wu, Shih-Hung Chen, Huai-Hsuan Tsai, Chih-Hung Cheng, Chien-Hua Tsai, Hsuan-Hsu Chen
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Publication number: 20050193587Abstract: A drying process for wafers includes positioning the wafers to be dried in a cleaning device full of isopropyl alcohol (IPA) vapor and replacing moisture out of the wafers with the IPA vapor. Gas steam including the IPA vapor is exhausted from the cleaning device into a scrubber, and the scrubber has at least a solvent therein for dissolving the IPA vapor and an exhaust outlet for discharging gas mixture of the IPA vapor and the solvent. A flow rate of the solvent in the scrubber is adjusted to increase a concentration of the IPA vapor in the cleaning device and thus obtain better uniformity for drying the wafers.Type: ApplicationFiled: March 3, 2004Publication date: September 8, 2005Inventors: Chien-Hua Tsai, Yi-Chin WU, Yen-Shen WEI
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Publication number: 20010014528Abstract: A method of manufacturing an unlanded via plug comprises the steps of providing a substrate having a conductive wire on the top surface of the substrate. A dielectric layer is formed on the substrate with a surface level between the top surface and the bottom surface of the conductive wire. An etching stop layer is formed over the substrate and the etching stop layer is planarized until exposing the surface of the conductive wire. Another dielectric layer is formed over the substrate, and then the dielectric layer is patterned to form a via hole and expose the conductive wire. Thereafter, the via hole is filled with a conductive material to form a via plug.Type: ApplicationFiled: December 17, 1998Publication date: August 16, 2001Inventor: CHIEN-HUA TSAI
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Patent number: 6265274Abstract: A semiconductor wafer comprises a silicon substrate, and a dielectric layer. A gate is formed on the dielectric layer. A first silicon oxide layer is uniformly formed on the semiconductor wafer. A first ion implantation process is performed to form two doped areas on the silicon substrate that are used as two lightly doped drains of a MOS transistor. A second silicon oxide layer is formed on the semiconductor wafer. A sacrificial layer is formed on the second silicon oxide layer. A first etching process is performed to remove the sacrificial layer on top of the gate, causing the gate to protrude from the remaining sacrificial layer for a predetermined height. A second etching process is performed to remove the first and second silicon oxide layers on the protruding portion of the gate. After removing the sacrificial layer completely, a silicon nitride layer is uniformly formed on the semiconductor wafer.Type: GrantFiled: November 1, 1999Date of Patent: July 24, 2001Assignee: United Microelectronics Corp.Inventors: Jui-Tsen Huang, Chien-Hua Tsai
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Patent number: 6204107Abstract: A method for forming a multi-layered liner on the sidewalls of a node contact opening includes the steps of providing a substrate having a dielectric layer thereon. The dielectric layer further includes a node contact opening that exposes a portion of the substrate. A first liner layer is then formed on the sidewalls of the node contact opening. Next, a second liner layer is formed over the first liner layer such that the first liner layer and the second liner layer together form a dual-layered liner. The first liner layer in contact with the dielectric layer has good insulation capacity while the second liner layer has good etch-resisting property.Type: GrantFiled: December 8, 1998Date of Patent: March 20, 2001Assignee: United Microelectronics Corp.Inventors: Kuo-Chi Lin, Kuen-Yow Lin, Chien-Hua Tsai, Kun-Chi Lin
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Patent number: 6191042Abstract: A method of fabricating a node contact opening includes formation of a dielectric layer on a substrate. An opening is formed with C4F8/Ar/CH2F2 as an etchant. A portion of the dielectric layer under the opening is etched with CHF3/CO as an etchant until the substrate is exposed. A node contact opening is formed.Type: GrantFiled: February 8, 1999Date of Patent: February 20, 2001Assignee: United Microelectronics Corp.Inventors: Chien-Hua Tsai, Kuo-Chi Lin
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Patent number: 6159833Abstract: The present invention provides a method of forming a contact hole in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a silicon--oxygen layer positioned on the silicon substrate, and a photoresist layer positioned on the silicon--oxygen layer. An anisotropic dry-etching process is performed to vertically remove the silicon--oxygen layer below the opening to a predetermined depth to form the contact hole which contains a polymer layer on its surface. A soft-etching process is performed to remove the polymer layer in the contact hole. The dry-etching process and soft-etching process are performed alternatively to vertically remove the silicon--oxygen layer under the contact hole until the surface of the silicon substrate can be reached through the contact hole.Type: GrantFiled: September 8, 1999Date of Patent: December 12, 2000Assignee: United Microelectronics Corp.Inventors: Chin-Hui Lee, Chien-Hua Tsai, Chih-Cheng Liu
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Patent number: 6150223Abstract: A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate.Type: GrantFiled: April 7, 1999Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Horng-Non Chern, Kun-Chi Lin, Alex Hou, Chien-Hua Tsai, Tsu-An Lin