Patents by Inventor Chien Huang

Chien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130293822
    Abstract: A display panel includes a pair of substrates, a pixel structure, and a display medium layer disposed between the pair of substrates. The pixel structure is disposed on one of the substrates, and includes first and second sub-pixels. The first sub-pixel includes a first pixel electrode, wherein the first pixel electrode has a first spacing in a first main region and has a second spacing in a first minor region, wherein the second spacing is smaller than the first spacing. The second sub-pixel includes a second pixel electrode, wherein the second pixel electrode has a third spacing in a second main region and has a fourth spacing in a second minor region, wherein the fourth spacing is larger than or equal to the third spacing, and wherein the first spacing is larger than the third spacing.
    Type: Application
    Filed: October 18, 2012
    Publication date: November 7, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Jen-Yang Chung, Kun-Cheng Tien, Ming-Huei Wu, Shin-Mei Gong, Chien-Huang Liao, Wen-Hao Hsu
  • Patent number: 8570817
    Abstract: A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: October 29, 2013
    Assignee: Elite Semiconductor Memory Technology, Inc.
    Inventor: Ming-Chien Huang
  • Publication number: 20130264681
    Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.
    Type: Application
    Filed: June 3, 2013
    Publication date: October 10, 2013
    Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
  • Publication number: 20130258078
    Abstract: A guide device includes a detection module, a processor, and an alarming module. The detection module captures road images in front of a blind person. The processor includes a calculating module and a comparing module. The calculating module calculates an actual height of an obstacle object of the road images. The comparing module compares the actual height with a pre-set critical height. The alarming module reminds the blind person that there is an obstacle object in front of the blind person when the actual height is greater than the critical height.
    Type: Application
    Filed: October 29, 2012
    Publication date: October 3, 2013
    Inventors: YU-CHIEN HUANG, GA-LANE CHEN
  • Publication number: 20130250620
    Abstract: A control circuit for reducing touch current of a power converter includes an auxiliary pin, a zero-crossing signal generator, a feedback pin, a frequency limiting signal generator, and a gate signal generator. The auxiliary pin receives a voltage corresponding to an auxiliary winding of the power converter. The zero-crossing signal generator generates a zero-crossing signal according to the voltage and a first reference voltage. The feedback pin receives a feedback voltage corresponding to an output voltage of the power converter. The frequency limiting signal generator generates a frequency limiting signal according to the feedback voltage and a second reference voltage. The frequency limiting signal limits the gate control signal to a predetermined frequency. The gate signal generator generates a gate control signal to a power switch of the power converter according to the frequency limiting signal and the zero-crossing signal.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 26, 2013
    Applicant: Leadtrend Technology Corp.
    Inventors: Kuo-Chien Huang, Chen-Lun Yang, Hsin-Hung Lu
  • Patent number: 8526244
    Abstract: An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 3, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Chien Huang
  • Publication number: 20130224952
    Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang
  • Patent number: 8514005
    Abstract: A circuit for generating multiphase clock signals and corresponding indication signals is provided. The circuit includes a multiphase clock generation circuit, a DLL circuit, a timing circuit, and a phase comparison circuit. The multiphase clock generation circuit receives an external clock to provide a plurality of first clock signals, phases of which differ from one another. The DLL circuit receives the external clock signal to provide a second clock signal. The timing circuit receives the second clock signal and a comparison signal to provide a plurality of indication signals. Each of the plurality of indication signals has rising edges which lead the rising edges of a corresponding one of the first clock signals. The phase comparison provides the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: August 20, 2013
    Assignee: Elite Semiconductor Memory Technology, Inc.
    Inventors: Ming-Chien Huang, Chien-Yi Chang
  • Patent number: 8498167
    Abstract: A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: July 30, 2013
    Assignee: Elite Semiconductor Memory Technology, Inc.
    Inventor: Ming-Chien Huang
  • Publication number: 20130188429
    Abstract: A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Chien Huang
  • Patent number: 8492017
    Abstract: A battery for a portable electronic device includes a recess, a number of electronic strips arranged on the bottom surface of the recess, and a number of latching slots defined in the sidewall of the recess.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: July 23, 2013
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Chih-Chien Huang
  • Patent number: 8493420
    Abstract: A driving method for determining target transmittance of a liquid crystal sub-pixel is provided. The liquid crystal sub-pixel has display regions, the liquid crystal sub-pixel displays the target transmittance when liquid crystal voltage applied to each display region is equal to one other and transmittance variation of liquid crystal layer in the liquid crystal sub-pixel is S0 when variation of LC voltage ?VLC occurs. The driving method includes selecting LC voltages in accordance with the target transmittance and area ratio of each display region; and applying each LC voltage to one of the display regions correspondingly, wherein transmittance of each display region is different from the target transmittance, the target transmittance is equal to sum of product of area ratio and transmittance of each display region, and transmittance variation of the liquid crystal layer in the liquid crystal sub-pixel is lower than S0 when variation of LC voltage ?VLC occurs.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: July 23, 2013
    Assignee: Au Optronics Corporation
    Inventors: Yu-Chieh Chen, Chien-Huang Liao, Pin-Miao Liu
  • Publication number: 20130181276
    Abstract: A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 18, 2013
    Applicant: YIELD MICROELECTRONICS CORP.
    Inventors: HSIN CHANG LIN, WEN CHIEN HUANG, YA-TING FAN
  • Publication number: 20130176215
    Abstract: A positioning signal transmitter module, adapted to use with a cursor-controlling device corporately for a cursor controlling, includes a light-guide element and at least one light source. The light-guide element has a light-emission surface and at least one light-incidence surface adjacent to the light-emission surface. The light source is disposed beside the light-incidence surface(s), and each light source is configured to provide a light signal to its corresponding light-incidence surface. The light signal emits out from the light-emission surface. Moreover, an electronic product with a cursor-controllable function using the aforementioned positioning signal transmitter module is also provided.
    Type: Application
    Filed: June 14, 2012
    Publication date: July 11, 2013
    Applicant: PixArt Imaging Inc.
    Inventors: Chao-Chien Huang, Chun-Yi Lu, Meng-Huan Hsieh
  • Publication number: 20130176523
    Abstract: In one aspect of the invention, a liquid crystal display device includes a pixel matrix having a plurality of pixels. Each pixel includes a first pixel electrode having a plurality of first pixel electrode stripes and a second pixel electrode having a plurality of second pixel electrode stripes. The first pixel electrode stripes and the second pixel electrode stripes are alternately placed to define a plurality of pitches therebetween. Each pixel is defined between two adjacent first pixel electrode and second pixel electrode stripes, and has a width. In one embodiment, the width of at least one of the pitches is different from that of the other pitches. In another embodiment, the width of each pitch is variable along the adjacent first pixel electrode and second pixel electrode stripes.
    Type: Application
    Filed: January 10, 2012
    Publication date: July 11, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Kuan-Yu Chen, Tien-Lun Ting, Chien-Huang Liao
  • Patent number: 8482992
    Abstract: A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM) is provided herein. A phase detector of the DLL compares an external clock signal with a feedback clock signal to generate a first control signal. A delay line circuit of the DLL delays the external clock signal according to the first control signal. A detector of the DRAM detects variations of the first control signal to determine a length of an enable period of an enable signal. The delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 9, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Chien Huang
  • Publication number: 20130168538
    Abstract: A light source determining apparatus for determining if a light source is a specific type light source is disclosed. The light source determining apparatus comprises: a light filtering device, comprising at least one first region and at least one second region, wherein the first region can pass only light with a specific frequency, where the second region can pass not only light with the specific frequency but also light with other frequencies; and a determining unit, for determining if the light source is the specific type light source, according to luminosity that the light source respectively generates for the first region and the second region.
    Type: Application
    Filed: July 17, 2012
    Publication date: July 4, 2013
    Inventors: Chia-Cheun Liang, Chao-Chien Huang, Chi-Yang Huang, Han-Ping Cheng
  • Patent number: 8476745
    Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 2, 2013
    Assignee: Mediatek Inc.
    Inventors: Chao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
  • Patent number: 8451884
    Abstract: An offset calibration method is provided. Two input terminals of an equalizer are switched to a common voltage at a first time point, wherein the equalizer generates a first equalized signal and a second equalized signal according to the common voltage. It is determined whether a first offset voltage is present in the equalizer according to the first and second equalized signals generated from the common voltage. If the first offset voltage is determined to be present in the equalizer, a first compensation voltage is provided to the equalizer.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: May 28, 2013
    Assignee: Mediatek Inc.
    Inventors: Chien-Ming Chen, Chih-Chien Huang, Shang-Yi Lin
  • Publication number: 20130132809
    Abstract: The present invention provides a structure and method for widget personalization and widget interaction, wherein user preference keys and user preference values are generated according to user profiles and binding configurations of a plurality of widgets, and wherein the keys and values of a widget are added to URL of the widget, whereby a personalized widget is attained after the widget is reloaded. The setting data of a widget, including a plurality of element values, are stored in a document object model (DOM). When relativities exist between widgets, the related element values are transferred from one widget to other widgets through a transfer module to replace the element values in DOM of the other widgets and update the other widgets.
    Type: Application
    Filed: March 20, 2012
    Publication date: May 23, 2013
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: CHIEN-CHAO TSENG, YU-HUA LU, CHENG-YUAN HO, YU-CHIEN HUANG