Abstract: A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure has a base layer, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner over the base layer. The method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers, and the base layer. The method further includes partially or completely removing the base layer to form a recess, forming a protective structure in the recess, and forming an epitaxial structure filling the opening. In addition, the method includes partially removing the substrate from a backside surface of the substrate to form a contact opening exposing the protective structure and extending towards the epitaxial structure. The method includes forming a backside conductive contact in the contact opening.

Abstract: An electronic device including a substrate with a trench and an inductor disposed on the substrate is provided. The inductor includes a first conductive layer and a second conductive layer. The first conductive layer is conformally disposed on the substrate. At least a portion of the first conductive layer is disposed in the trench. The first conductive layer has a first end portion and a second end portion. The second conductive layer is conformally disposed on the first conductive layer. The second conductive layer has a first end portion and a second end portion on the first end portion of the first conductive layer and the second end portion of the first conductive layer, respectively. The first end portion of the second conductive layer is electrically connected with the second end portion of the first conductive layer.

Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.

Abstract: A method of qualifying semiconductor wafer processing includes: illuminating a semiconductor wafer simultaneously with source light having wavelengths in a plurality of wavebands, including at least a first waveband and a second waveband, the second waveband being different from the first waveband; separating light reflected from the semiconductor wafer as a result of said illuminating, the separating dividing the reflected light according to waveband; generating a first image of the semiconductor wafer based on reflected light separated into the first waveband; and, generating a second image of the semiconductor wafer base on reflected light separated into the second waveband.

Abstract: A method of qualifying semiconductor wafer processing includes: illuminating a semiconductor wafer simultaneously with source light having wavelengths in a plurality of wavebands, including at least a first waveband and a second waveband, the second waveband being different from the first waveband; separating light reflected from the semiconductor wafer as a result of said illuminating, the separating dividing the reflected light according to waveband; generating a first image of the semiconductor wafer based on reflected light separated into the first waveband; and, generating a second image of the semiconductor wafer base on reflected light separated into the second waveband.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A system configured to detect defects on a wafer is provided. The system includes an inspection subsystem configured to acquire scan data of a target region on the wafer. The target region comprises a plurality of circuit layout streaming data on the wafer and the defects in proximity to the circuit layout streaming data or in the circuit layout streaming data. A graphic design subsystem (GDS) is configured to store a map of circuit layout streaming data of the wafer. A software tool for designing electronic systems is configured to label the scan data with attributes from the map of circuit layout streaming data. A decision subsystem is configured to qualify the process based on a predetermined defect level from the labeled scan data by using a multi-dimension clustering method, wherein the predetermined defect level is an accumulated defect formed on the semiconductor wafer during processing.

Abstract: A method of qualifying semiconductor wafer processing includes: illuminating a semiconductor wafer simultaneously with source light having wavelengths in a plurality of wavebands, including at least a first waveband and a second waveband, the second waveband being different from the first waveband; separating light reflected from the semiconductor wafer as a result of said illuminating, the separating dividing the reflected light according to waveband; generating a first image of the semiconductor wafer based on reflected light separated into the first waveband; and, generating a second image of the semiconductor wafer base on reflected light separated into the second waveband.

Abstract: A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A defect detecting method, a defect detecting system, and a non-transitory computer-readable medium are provided. The defect detecting method includes applying a rank filter to multiple scan images of consecutive dies of a reference wafer scanned by a wafer inspection tool to obtain multiple reference die images; collecting multiple target die images of a target die of a target wafer scanned by the wafer inspection tool; comparing the target die images with the reference die images to detect multiple defects according to differences of pixel values of corresponding pixels in the target die images and the reference die images; and excluding multiple common defects from the detected defects to detect at least one mask defect printed on the target wafer, where the common defects are obtained by the wafer inspection tool performing a wafer inspection on the target wafer.

Abstract: A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A defect inspection method and a defect inspection system are provided. In the method, a plurality of candidate defect images are retrieved from inspection images obtained by at least one optical inspection tool performing hot scans on at least one wafer and a plurality of attributes are extracted from the inspection images. A random forest classifier including a plurality of decision trees for classifying the candidate defect images is created, wherein the decision trees are built with different subset of the attributes and the candidate defect images. A plurality of candidate defect images are retrieved from the optical inspection tool in runtime and applied to the decision trees, and classified into nuisance images and real defect images according to votes of the decision trees in which the nuisance images are filtered out. The real defect images with the votes over a confidence value are sampled for microscopic review.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A defect inspection method and a defect inspection system are provided. In the method, a plurality of candidate defect images are retrieved from inspection images obtained by at least one optical inspection tool performing hot scans on at least one wafer and a plurality of attributes are extracted from the inspection images. A random forest classifier including a plurality of decision trees for classifying the candidate defect images is created, wherein the decision trees are built with different subset of the attributes and the candidate defect images. A plurality of candidate defect images are retrieved from the optical inspection tool in runtime and applied to the decision trees, and classified into nuisance images and real defect images according to votes of the decision trees in which the nuisance images are filtered out. The real defect images with the votes over a confidence value are sampled for microscopic review.

Abstract: A defect detecting method, a defect detecting system, and a non-transitory computer-readable medium are provided. The defect detecting method includes applying a rank filter to multiple scan images of consecutive dies of a reference wafer scanned by a wafer inspection tool to obtain multiple reference die images; collecting multiple target die images of a target die of a target wafer scanned by the wafer inspection tool; comparing the target die images with the reference die images to detect multiple defects according to differences of pixel values of corresponding pixels in the target die images and the reference die images; and excluding multiple common defects from the detected defects to detect at least one mask defect printed on the target wafer, where the common defects are obtained by the wafer inspection tool performing a wafer inspection on the target wafer.

Abstract: One embodiment relates to a method of inspecting an array of cells on a substrate. A reference image is generated using a cell image that was previously determined to be defect free. A reference contour image which includes contours of the reference image is also generated. The reference contour image is used to detect defects in the array of cells on the substrate. Another embodiment relates to a system for detecting defects in an array on a substrate. Other embodiments, aspects and features are also disclosed.

Abstract: One embodiment relates to a method of inspecting an array of cells on a substrate. A reference image is generated using a cell image that was previously determined to be defect free. A reference contour image which includes contours of the reference image is also generated. The reference contour image is used to detect defects in the array of cells on the substrate. Another embodiment relates to a system for detecting defects in an array on a substrate. Other embodiments, aspects and features are also disclosed.