Patents by Inventor Chien-Hui Chen
Chien-Hui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9478469Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.Type: GrantFiled: March 16, 2015Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Lin Chuang, Chien-Hui Chen, Wei-Pin Changchien, Chin-Her Chien, Nan-Hsin Tseng
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Publication number: 20160307779Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.Type: ApplicationFiled: April 13, 2016Publication date: October 20, 2016Inventors: Yu-Tung CHEN, Quan-Qun SU, Chuan-Jin SHIU, Chien-Hui CHEN, Hsiao-Lan YEH, Yen-Shih HO
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Patent number: 9437478Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: September 6, 2016Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen, Ho-Yin Yiu
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Patent number: 9425134Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: August 23, 2016Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 9355970Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: GrantFiled: December 3, 2015Date of Patent: May 31, 2016Assignee: XINTEC INC.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 9355975Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: May 31, 2016Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen, Chi-Chang Liao
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Patent number: 9349710Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.Type: GrantFiled: October 1, 2014Date of Patent: May 24, 2016Assignee: XINTEC INC.Inventors: Chien-Hui Chen, Tsang-Yu Liu, Chun-Wei Chang, Chia-Ming Cheng
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Patent number: 9318461Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.Type: GrantFiled: April 17, 2014Date of Patent: April 19, 2016Assignee: XINTEC INC.Inventors: Chun-Wei Chang, Kuei-Wei Chen, Chia-Ming Cheng, Chia-Sheng Lin, Chien-Hui Chen, Tsang-Yu Liu
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Patent number: 9305843Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.Type: GrantFiled: January 13, 2015Date of Patent: April 5, 2016Assignee: XINTEC INC.Inventors: Bing-Siang Chen, Chien-Hui Chen, Shu-Ming Chang, Tsang-Yu Liu, Yen-Shih Ho
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Publication number: 20160086896Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: ApplicationFiled: December 3, 2015Publication date: March 24, 2016Inventors: Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Patent number: 9275963Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.Type: GrantFiled: March 6, 2014Date of Patent: March 1, 2016Assignee: XINTEC INC.Inventors: Yung-Tai Tsai, Shu-Ming Chang, Chun-Wei Chang, Chien-Hui Chen, Tsang-Yu Liu, Yen-Shih Ho
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Patent number: 9209124Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: GrantFiled: August 12, 2013Date of Patent: December 8, 2015Assignee: XINTEC INC.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 9184092Abstract: A method for forming a chip package, by providing a substrate having a plurality of conducting pads below a lower surface, and a dielectric layer located between the conducting pads, forming a recess in an upper surface of the substrate, forming a hole extending through the bottom of the recess, forming an insulating layer on the sidewall of the recess and in the hole, exposing a portion of the conducting pads through the insulating layer, and forming a conducting layer on the insulating layer and through the hole to contact with the conducting pads.Type: GrantFiled: March 14, 2014Date of Patent: November 10, 2015Assignee: XINTEC INC.Inventors: Yu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Long-Sheng Yeou
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Patent number: 9165890Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.Type: GrantFiled: July 15, 2013Date of Patent: October 20, 2015Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Shih-Chin Chen, Yi-Ming Chang, Chien-Hui Chen, Chia-Ming Cheng, Wei-Luen Suen, Chen-Han Chiang
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Publication number: 20150187666Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.Type: ApplicationFiled: March 16, 2015Publication date: July 2, 2015Inventors: Yi-Lin Chuang, Chien-Hui Chen, Wei-Pin Changchien, Chin-Her Chien, Nan-Hsin Tseng
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Publication number: 20150162245Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.Type: ApplicationFiled: January 13, 2015Publication date: June 11, 2015Inventors: Bing-Siang CHEN, Chien-Hui CHEN, Shu-Ming CHANG, Tsang-Yu LIU, Yen-Shih HO
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Patent number: 9024437Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.Type: GrantFiled: June 15, 2012Date of Patent: May 5, 2015Inventors: Yu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Yen-Shih Ho
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Publication number: 20150097299Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.Type: ApplicationFiled: October 1, 2014Publication date: April 9, 2015Inventors: Chien-Hui CHEN, Tsang-Yu LIU, Chun-Wei CHANG, Chia-Ming CHENG
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Patent number: 8981842Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.Type: GrantFiled: October 25, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Lin Chuang, Chien-Hui Chen, Wei-Pin Changchien, Chin-Her Chien, Nan-Hsin Tseng
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Patent number: 8963312Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: February 24, 2015Assignee: Xintec, Inc.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen