Patents by Inventor Chien-Hung Wang

Chien-Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Patent number: 11967594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240128139
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate along a predetermined direction for being electrically coupled to each other, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer is formed with at least one type of a buffering cavity, wave-shaped slots, and rectangular slots, which penetrate therethrough along the predetermined direction. The buffering cavity can be located in the adhesive layer, and any one type of the wave-shaped slots and the rectangular slots can be respectively recessed in an inner side and an outer side of the adhesive layer. A minimum width of the adhesive layer is greater than or equal to 50% of a predetermined width between the inner side and the outer side.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: WEI-LI WANG, JYUN-HUEI JIANG, WEN-FU YU, BAE-YINN HWANG, CHIEN-HUNG LIN
  • Publication number: 20240128291
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEI-LI WANG, WEN-FU YU, BAE-YINN HWANG
  • Publication number: 20240128233
    Abstract: A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, WEN-FU YU, BAE-YINN HWANG, WEI-LI WANG, CHIEN-HUNG LIN
  • Publication number: 20240114688
    Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 4, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
  • Publication number: 20240105644
    Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 28, 2024
    Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
  • Publication number: 20240084621
    Abstract: A security lock has a fixing element and at least one hook. The fixing element is mounted in a security slot of an electronic device. The hook is capable of moving axially with respect to the fixing element, and the hook moves radially outward along a guiding structure of the fixing element to engage with the security slot, the fixing element stays static, i.e., without moving and rotating as the hook is moving. Therefore, the security lock won't press the security slot, and further prevents damage to the security slot caused by frequently or constantly loaded with the security lock. Furthermore, without moving and rotating in a mounting process of the security lock, the fixing element holds the hook to steadily engage with the security slot, and thus an overall anti-pulling and anti-pushing performances are enhanced.
    Type: Application
    Filed: July 17, 2023
    Publication date: March 14, 2024
    Inventors: Chien-Hung WU, Chia-Hung WANG
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240087974
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240072411
    Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Applicant: Pegatron Corporation
    Inventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
  • Patent number: 11130107
    Abstract: A method includes mixing a first deionized water (DI) water from a first pipe and a second DI water from a second pipe in a merging pipe that is in fluid communication with the first pipe and the second pipe. An electrical resistivity of the first DI water is different from an electrical resistivity of the second DI water. A mixture of the first DI water and the second DI water is applied from the merging pipe onto a wafer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Wei-Chang Cheng, Chien-Hung Wang
  • Patent number: 11035619
    Abstract: A drainage device includes a tank, a pipe and an air duct. The tank has a base plate and at least one first wall. The first wall is disposed on the base plate. The base plate and the first wall define a space. The pipe defines a channel. The pipe connects with the base plate. The channel communicates with the space. The air duct is disposed partially in the space and partially in the channel. There exists at least one gap between an outer surface of the air duct and an inner surface of the pipe.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chang Cheng, Chi-Hung Liao, Chien-Hung Wang, Guan-Yu Lin, Yung-Yao Lee
  • Publication number: 20210016316
    Abstract: A method of preventing drippage in a fluid dispensing system. The fluid dispensing system includes a first automatic control valve (ACV), an input of the first ACV connected to fluid-source of fluid, the first ACV having positions ranging from fully closed to fully open, and a second ACV, an input of the second ACV being connected to an output of the first ACV, and an output of the second ACV being connected to a nozzle, the second ACV having positions ranging from fully closed to fully open. The method includes generating a first proxy signal representing at least a first indirect measure of a position of the first ACV. The method includes recognizing, based on at least the first proxy signal that a failure state exists in which the first ACV has failed to close. The method includes causing the second ACV to close when the failure state exists.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Chien-Hung WANG, Chun-Chih LIN, Chi-Hung LIAO, Yung-Yao LEE, Wei Chang CHENG
  • Patent number: 10792697
    Abstract: A drippage prevention system including: a first automatic control valve (ACV), an input of the first ACV fluidically connected to a source of fluid to be dispensed, the first ACV having a position ranging from fully closed to fully open; a second ACV, an input of the second ACV being fluidically connected to the output of the first ACV, and an output of the second ACV being fluidically connected to a nozzle, the second ACV having positions ranging from fully closed to fully open; a proxy sensor configured to generate a proxy signal representing an indirect measure of a position of the first ACV; and a controller electrically connected to the first and second ACVs and the proxy sensor, the controller being configured to cause the second ACV to close based on the proxy signal and thereby stop flow of the liquid to the nozzle.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hung Wang, Chun-Chih Lin, Chi-Hung Liao, Yung-Yao Lee, Wei Chang Cheng
  • Publication number: 20200061559
    Abstract: A method includes mixing a first deionized water (DI) water from a first pipe and a second DI water from a second pipe in a merging pipe that is in fluid communication with the first pipe and the second pipe. An electrical resistivity of the first DI water is different from an electrical resistivity of the second DI water. A mixture of the first DI water and the second DI water is applied from the merging pipe onto a wafer.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung LIAO, Wei-Chang CHENG, Chien-Hung WANG
  • Patent number: 10464032
    Abstract: A system for providing deionized (DI) water with a dynamic electrical resistivity is provided. The system includes plural DI water sources, source pipes, flow control devices, a merging pipe and a flow controller. The DI water sources respectively have different electrical resistivities. The source pipes are respectively connected to the DI water sources in a one-to-one manner. The flow control devices are respectively disposed in the source pipes in a one-to-one manner. The merging pipe joins the source pipes. The flow controller includes a resistivity sensor disposed in the merging pipe, and the flow controller is configured to control a flowrate of the DI water through the source pipes.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Wei-Chang Cheng, Chien-Hung Wang
  • Publication number: 20180333738
    Abstract: A drippage prevention system including: a first automatic control valve (ACV), an input of the first ACV fluidically connected to a source of fluid to be dispensed, the first ACV having a position ranging from fully closed to fully open; a second ACV, an input of the second ACV being fluidically connected to the output of the first ACV, and an output of the second ACV being fluidically connected to a nozzle, the second ACV having positions ranging from fully closed to fully open; a proxy sensor configured to generate a proxy signal representing an indirect measure of a position of the first ACV; and a controller electrically connected to the first and second ACVs and the proxy sensor, the controller being configured to cause the second ACV to close based on the proxy signal and thereby stop flow of the liquid to the nozzle.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Inventors: Chien-Hung WANG, Chun-Chih LIN, Chi-Hung LIAO, Yung-Yao LEE, Wei Chang CHENG
  • Publication number: 20180304215
    Abstract: A system for providing deionized (DI) water with a dynamic electrical resistivity is provided. The system includes plural DI water sources, source pipes, flow control devices, a merging pipe and a flow controller. The DI water sources respectively have different electrical resistivities. The source pipes are respectively connected to the DI water sources in a one-to-one manner. The flow control devices are respectively disposed in the source pipes in a one-to-one manner. The merging pipe joins the source pipes. The flow controller includes a resistivity sensor disposed in the merging pipe, and the flow controller is configured to control a flowrate of the DI water through the source pipes.
    Type: Application
    Filed: June 20, 2017
    Publication date: October 25, 2018
    Inventors: Chi-Hung LIAO, Wei-Chang CHENG, Chien-Hung WANG
  • Publication number: 20180164839
    Abstract: A drainage device includes a tank, a pipe and an air duct. The tank has a base plate and at least one first wall. The first wall is disposed on the base plate. The base plate and the first wall define a space. The pipe defines a channel. The pipe connects with the base plate. The channel communicates with the space. The air duct is disposed partially in the space and partially in the channel. There exists at least one gap between an outer surface of the air duct and an inner surface of the pipe.
    Type: Application
    Filed: March 29, 2017
    Publication date: June 14, 2018
    Inventors: Wei-Chang Cheng, Chi-Hung Liao, Chien-Hung Wang, Guan-Yu Lin, Yung-Yao Lee