Abstract: A grinding apparatus and a crystal orientation adjustment fixture thereof are provided. The crystal orientation adjustment fixture includes a fixing seat, an adjustment body, a first adjustment component, and a universal mandrel module. The adjustment body is assembled to the fixing seat through a rear end surface thereof. The adjustment body has a universal slot recessed in a front end surface thereof and a first adjustment slot formed along an adjustment direction, and a bottom of the first adjustment slot corresponds in position to the fixing seat. The first adjustment component is movably assembled in the first adjustment slot along the adjustment direction and abuts against the fixing seat. The universal mandrel module is rotatably assembled in the universal slot. The first adjustment component is adjustable along the adjustment direction to move the adjustment body relative to the fixing seat along the adjustment direction.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A display device includes first and second display modules and first and second turning pieces that include a first coupling piece, a first turning piece, a second turning piece, and a third turning piece, a second coupling piece and a guiding device. When the first and second display modules are switched between folding and unfolding, the first turning piece pivots relative to the first coupling piece and the second turning piece, and the third turning piece pivots relative to the second coupling piece and the second turning piece. When the display module is switched from folded to unfolded, the other side of the first display module relative to the side is pulled, the side of the first display module is guided by one end of the guiding device and slides to the other end, the first and second display modules are symmetrically unfolded with the side edge as the center.

Abstract: A composite material structure, including an outer layer, an inner layer, and a middle layer, is provided. The outer layer includes a metallic material. The inner layer includes a fiber material and a resin material. The outer layer has a first thickness, the inner layer has a second thickness, and the first thickness is different from the second thickness. The middle layer includes an adhesive material and is disposed between the outer layer and the inner layer. Two opposite surfaces of the middle layer are respectively in direct contact with the outer layer and the inner layer. A manufacturing method of the composite material structure is also provided.

Abstract: A lens assembly includes a first lens group, a second lens group, a third lens group, a fourth lens group, and a reflective element. The first lens group is with refractive power. The second lens group is with positive refractive power. The third lens group is with positive refractive power. The fourth lens group is with refractive power. The reflective element includes a reflective surface. A light from an object sequentially passes through the first lens group, the second lens group, the third lens group, and the fourth lens group to an image side along an axis. The reflective element is disposed between an object side and the image side along the axis. Intervals of the lens groups are changeable when the lens assembly zooms from a wide-angle end to a telephoto end.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A speaker module, including: a speaker enclosure, including: a recessed portion; a transducer, including: a top surface; a bottom surface; a perimeter surface positioned between the top surface and the bottom surface; a rubber cap including: a top side; a bottom side; and edges extending between the top side and the bottom side, wherein the edges define an inside perimeter of the rubber cap and include a slot extending along the inside perimeter of the rubber cap, wherein, the transducer is coupled to the rubber cap such that the rubber cap surrounds the transducer and the perimeter surface of the transducer is positioned within the slot of the plurality of edges of the rubber cap, wherein, the transducer is coupled to the speaker enclosure such that the transducer is positioned within the recessed portion of the speaker enclosure and the rubber cap is positioned between the transducer and the speaker.

Abstract: Some implementations described herein provide an inductor device formed in a substrate of a semiconductor device including an integrated circuit device. The inductor device may use one or more conduction layers that are included in the substrate. Furthermore, the inductor device may be electrically coupled to the integrated circuit device. By forming the inductor device in the substrate of the semiconductor device, an electrical circuit including the inductor device and the integrated circuit device may be formed within a single semiconductor device.

Abstract: Provided are a liquid crystal polymer (LCP) film and a laminate comprising the same. The LCP film has a first surface and a second surface opposite each other, and a ratio of a ten-point mean roughness relative to a maximum height (Rz/Ry) of the first surface is from 0.30 to 0.62. By controlling Rz/Ry of at least one surface of the LCP film, the peel strength of the LCP film stacked to a metal foil can be increased, and the laminate comprising the same can still maintain the merit of low insertion loss.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC is manufactured by forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate, filling an isolation material in the isolation trench and the logic device trench, removing the isolation material from the logic device trench, forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench, and forming first and second source/drain regions in the substrate on opposite sides of the logic device trench. The isolation material is kept in the isolation trench to form an isolation structure.

Abstract: An electronic device includes a metal back cover and an antenna module. The metal back cover includes a slit. The antenna module is separated from the metal back cover and disposed far away from the slit. The antenna module includes an antenna radiator, a first ground radiator, and a connection radiator. The antenna radiator includes a first section, a second section, and a third section that are sequentially connected and form bends, and the first section has a feeding end. A first slot is formed between the first ground radiator, the first section, the second section, and a part of the third section. A width and length of the first slot are associated with a center frequency and impedance matching of a high frequency band.

Abstract: An electronic device, including a metal back cover, a front cover, a metal wall, and at least one antenna radiator, is provided. The front cover covers the metal back cover and includes a frame area. The metal wall is disposed between the metal back cover and the front cover, and forms a metal cavity corresponding to the frame area together with the metal back cover. Each of the at least one antenna radiator is disposed in the metal cavity, is connected to a first side wall of the metal back cover, and is spaced apart from the metal wall by a distance.

Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first substrate and through vias formed through the first substrate. The package further includes redistribution layers formed over the first substrate and connected to the through vias and a first pillar layer formed over the redistribution layers. The package further includes a first barrier layer formed over the first pillar layer and a first cap layer formed over the first barrier layer. The package further includes an underfill layer formed over the redistribution layers and surrounding the first pillar layer, the first barrier layer, and the first cap layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first sidewall surface of the first pillar layer and a second sidewall surface of the first cap layer.

Abstract: A dual-code lock core is provided, including a first unlocking component, a code wheel, and a second unlocking component. When the code wheel rotates to a first unlocking position, the first unlocking component may move to unlock the dual-code lock core; and when the code wheel rotates to a second unlocking position, the second unlocking component may move to unlock the dual-code lock core.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.

Abstract: The invention discloses an etching solution and a manufacturing method of a display panel. The method includes following steps: providing a first substrate; forming a conductive layer stack including a first sub-layer, a second sub-layer and a third sub-layer, each of the first sub-layer and the second sub-layer includes a transparent conductive material including indium-containing oxide, the third sub-layer is disposed between the first sub-layer and the second sub-layer, and the third sub-layer includes silver or silver alloy; performing an etching process, an etching solution is used to etch the first sub-layer, the second sub-layer and the third sub-layer to form a first patterned sub-layer, a second patterned sub-layer and a third patterned sub-layer, and the etching solution includes 1 to 2.6 wt % of nitric acid, 35 to 45 wt % of acetic acid, 35 to 45 wt % of phosphoric acid and a remaining amount of water.

Abstract: A security lock has a fixing element and at least one hook. The fixing element is mounted in a security slot of an electronic device. The hook is capable of moving axially with respect to the fixing element, and the hook moves radially outward along a guiding structure of the fixing element to engage with the security slot, the fixing element stays static, i.e., without moving and rotating as the hook is moving. Therefore, the security lock won't press the security slot, and further prevents damage to the security slot caused by frequently or constantly loaded with the security lock. Furthermore, without moving and rotating in a mounting process of the security lock, the fixing element holds the hook to steadily engage with the security slot, and thus an overall anti-pulling and anti-pushing performances are enhanced.

Abstract: A heat dissipation substrate includes heat dissipation blocks, an insulation filling structure, a first insulating layer, and a first circuit layer. Each heat dissipation block includes a first surface and a second surface opposite to the first surface. The insulation filling structure is disposed between the heat dissipation blocks to laterally connect the heat dissipation blocks. A first insulating surface of the insulation filling structure is substantially coplanar with the first surface of the heat dissipation block. A second insulating surface of the insulation filling structure is substantially coplanar with the second surface of the heat dissipation block. The first insulating layer is disposed on the first surface. The first circuit layer is disposed on the first insulating layer and penetrates the first insulating layer to be connected with the heat dissipation blocks. A thickness of the heat dissipation blocks is greater than a thickness of the first circuit layer.