Patents by Inventor CHIEN-I CHOU

CHIEN-I CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230412201
    Abstract: A transmitter includes an analog transmission circuit, a power amplifier, a voltage detector, a comparator, and a control circuit. The analog transmission circuit is configured to provide a first gain to a first analog signal, so as to generate a second analog signal. The power amplifier is configured to provide a second gain to the second analog signal, so as to generate an output signal to an antenna. The voltage detector is configured to detect a voltage level of the second analog signal. The comparator is configured to generate an indication signal according to the voltage level and a reference level. The control circuit is configured to adjust the first gain of the analog transmission circuit according to the indication signal.
    Type: Application
    Filed: May 16, 2023
    Publication date: December 21, 2023
    Inventor: CHIEN-I CHOU
  • Publication number: 20230188224
    Abstract: A transmitting circuit, which includes a power amplifier, a processing circuit, and a signal strength indicator circuit. The power amplifier is configured to amplify an input signal according to a power gain of the power amplifier to generate an output signal. The processing circuit is configured to adjust the power gain according to an indicating signal. The signal strength indicator circuit has a plurality of power detection ranges. The signal strength indicator circuit is configured to uses one of the plurality of power detection ranges to detect a power of the output signal to generate the indicating signal.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 15, 2023
    Inventor: CHIEN-I CHOU
  • Patent number: 11671060
    Abstract: The present invention discloses a power amplification apparatus having a digital pre-distortion mechanism that includes a digital pre-distortion circuit and a power amplifier. The digital pre-distortion circuit receives an original digital signal having an original real part and an original imaginary part. When a first one and a second one of the original real part and the original imaginary part are a low state voltage level and a high state voltage level, the digital pre-distortion circuit outputs a first and a second voltage levels equivalent to the low state voltage level as a first pre-distortion part and directly outputs the second one of the original real part and the original imaginary part as a second pre-distortion part to generate an input signal having an input real part and an input imaginary part each corresponding to one of the first pre-distortion part and the second pre-distortion part. The power amplifier receives the input signal to perform power amplification to generate an output signal.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: June 6, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hang Liu, Wen-Shan Wang, Chien-I Chou, Kiat-Seng Yeo
  • Patent number: 11601206
    Abstract: A signal strength indicator circuit, configured to detect a power of an output signal outputted by a power amplifier, includes a voltage gain circuit, a current gain circuit, a multiplier, and a buffer stage. The voltage gain circuit provides a first gain to the output signal to generate a first value of an indicating voltage when a voltage of the output signal is not greater than a threshold, and provides a second gain to generate a second value of the indicating voltage when the voltage of the output signal is greater than the threshold. The first gain is greater than the second gain. The current gain circuit generates an indicating current according to an input signal corresponding to the output signal. The multiplier multiplies the indicating voltage and the indicating current to generate an indicating power. The buffer stage converts the indicating power to the indicating signal.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: March 7, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chien-I Chou
  • Publication number: 20220393647
    Abstract: A power detector device includes a power detector circuit, a filter circuit, and a calibration circuitry. The power detector circuit is configured to detect a first signal to generate a second signal. The filter circuit is configured to filter the second signal to generate a third signal. The calibration circuitry is configured to determine first signal strength information in response to the third signal, adjust a gain of the power detector circuit to obtain second signal strength information, and combine the first signal strength information and the second signal strength information, in order to calibrate a detection power range of the power detector circuit to be linear.
    Type: Application
    Filed: May 16, 2022
    Publication date: December 8, 2022
    Inventors: CHIEN-I CHOU, LING LEE
  • Publication number: 20220385379
    Abstract: A signal strength indicator circuit, configured to detect a power of an output signal outputted by a power amplifier, includes a voltage gain circuit, a current gain circuit, a multiplier, and a buffer stage. The voltage gain circuit provides a first gain to the output signal to generate a first value of an indicating voltage when a voltage of the output signal is not greater than a threshold, and provides a second gain to generate a second value of the indicating voltage when the voltage of the output signal is greater than the threshold. The first gain is greater than the second gain. The current gain circuit generates an indicating current according to an input signal corresponding to the output signal. The multiplier multiplies the indicating voltage and the indicating current to generate an indicating power. The buffer stage converts the indicating power to the indicating signal.
    Type: Application
    Filed: July 15, 2021
    Publication date: December 1, 2022
    Inventor: CHIEN-I CHOU
  • Publication number: 20220060154
    Abstract: The present invention discloses a power amplification apparatus having a digital pre-distortion mechanism that includes a digital pre-distortion circuit and a power amplifier. The digital pre-distortion circuit receives an original digital signal having an original real part and an original imaginary part. When a first one and a second one of the original real part and the original imaginary part are a low state voltage level and a high state voltage level, the digital pre-distortion circuit outputs a first and a second voltage levels equivalent to the low state voltage level as a first pre-distortion part and directly outputs the second one of the original real part and the original imaginary part as a second pre-distortion part to generate an input signal having an input real part and an input imaginary part each corresponding to one of the first pre-distortion part and the second pre-distortion part. The power amplifier receives the input signal to perform power amplification to generate an output signal.
    Type: Application
    Filed: April 8, 2021
    Publication date: February 24, 2022
    Inventors: HANG LIU, WEN-SHAN WANG, CHIEN-I CHOU, KIAT-SENG YEO
  • Patent number: 10075136
    Abstract: The present invention discloses a power amplifier capable of adaptively operating in one of an energy efficient mode and a high output power mode. An embodiment of the power amplifier includes a first transistor, a second transistor, a first bias element, a second bias element, a third bias element and a plurality of switches. In the energy efficient mode, by the control over the on/off states of the switches, an inverter type power amplifier is realized with the first transistor, the second transistor, the second bias element and the third bias element. In the high output power mode, by the control over the on/off states of the switches, a common source amplifier or a common emitter amplifier is realized with the second transistor and the first bias element.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 11, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-I Chou, Ka-Un Chan
  • Publication number: 20180152152
    Abstract: The present invention discloses a power amplifier capable of adaptively operating in one of an energy efficient mode and a high output power mode. An embodiment of the power amplifier includes a first transistor, a second transistor, a first bias element, a second bias element, a third bias element and a plurality of switches. In the energy efficient mode, by the control over the on/off states of the switches, an inverter type power amplifier is realized with the first transistor, the second transistor, the second bias element and the third bias element. In the high output power mode, by the control over the on/off states of the switches, a common source amplifier or a common emitter amplifier is realized with the second transistor and the first bias element.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 31, 2018
    Inventors: CHIEN-I CHOU, KA-UN CHAN