Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.

Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: A phototherapy device includes a base, at least one light conversion device and a light source module. The base has an installation slot. The light conversion device is detachably arranged in the installation slot. Each light conversion device includes a plurality of light conversion patterns. The light source module is arranged on a side of the base and configured to provide an excitation beam to the light conversion patterns, so that each of the light conversion patterns emits a converted beam. In this way, the light conversion device of the phototherapy device can be replaced according to the user's needs.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes overlapping an active region with a plurality of gate regions, thereby defining a program transistor and a read transistor of a one-time-programmable (OTP) bit, overlapping a through via region with a gate region of the plurality of gate regions or with the active region, and overlapping the through via region with a metal region of a back-side metal layer.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.

Abstract: The present disclosure provides a conversion circuit including a power supply module, positive and negative input terminals, positive and negative output terminals, a switch, an inductor, input and output capacitors, and a controller. The power supply module converts an AC power for providing three potentials on three power supply terminals respectively. The potential on the first power supply terminal is higher than the potential on the second power supply terminal, which is higher than the potential on the third power supply terminal. The positive and negative input terminals are electrically connected to the first and third power supply terminals respectively, and a voltage therebetween is an input voltage. The negative output terminal is electrically connected to the third power supply terminal. The controller is electrically connected to the positive input terminal, the second power supply terminal and the switch. A voltage across the controller is lower than the input voltage.

Abstract: The present disclosure provides a conversion circuit including a power supply module, positive and negative input terminals, positive and negative output terminals, a switch, an inductor, input and output capacitors, and a controller. The power supply module converts an AC power for providing three potentials on three power supply terminals respectively. The potential on the first power supply terminal is higher than the potential on the second power supply terminal, which is higher than the potential on the third power supply terminal. The positive and negative input terminals are electrically connected to the first and third power supply terminals respectively, and a voltage therebetween is an input voltage. The negative output terminal is electrically connected to the third power supply terminal. The controller is electrically connected to the positive input terminal, the second power supply terminal and the switch. A voltage across the controller is lower than the input voltage.

Abstract: A method for driving a display device is provided. The display device includes a first driving circuit and a pixel array. The driving method includes the following step. In a first mode, by using the first driving circuit, a first light emission start signal is received to drive the pixel array. The first light emission start signal includes a plurality of first pulses, and duration of each of the first pulses is respectively overlapped with at least a part of a period of each of a first frame and at least one second frame. In a second mode, by using the first driving circuit, a second light emission start signal is received to drive the pixel array. The second light emission start signal includes a second pulse. Duration of the second pulse is overlapped with at least a part of a period of the first frame, and the second light emission start signal remains at a first level in a period of the at least one second frame.

Abstract: An OLED panel includes a data driver and an AMOLED. The data driver receives an input voltage and the data driver may generate a data output signal. The AMOLED may receive a positive supply voltage and a negative supply voltage and emit light according to the data output signal. In addition, the input voltage and the positive supply voltage are substantially the same.

Abstract: A method for driving a display device is provided. The display device includes a first driving circuit and a pixel array. The driving method includes the following step. In a first mode, by using the first driving circuit, a first light emission start signal is received to drive the pixel array. The first light emission start signal includes a plurality of first pulses, and duration of each of the first pulses is respectively overlapped with at least a part of a period of each of a first frame and at least one second frame. In a second mode, by using the first driving circuit, a second light emission start signal is received to drive the pixel array. The second light emission start signal includes a second pulse. Duration of the second pulse is overlapped with at least a part of a period of the first frame, and the second light emission start signal remains at a first level in a period of the at least one second frame.

Abstract: An OLED panel includes a data driver and an AMOLED. The data driver receives an input voltage and the data driver may generate a data output signal. The AMOLED may receive a positive supply voltage and a negative supply voltage and emit light according to the data output signal. In addition, the input voltage and the positive supply voltage are substantially the same.

Abstract: Disclosed herein is a bispecific peptide conjugate comprising an epidermal growth factor receptor (EGFR) targeting peptide, an ?v?3 integrin targeting peptide, and a linker, where the linker is conjugated respectively to the EGFR targeting peptide and the ?v?3 integrin targeting peptide.

Abstract: A paper feeding device includes a pickup mechanism, a conveying mechanism disposed behind the pickup mechanism, a separation mechanism disposed behind the conveying mechanism, a feeding mechanism disposed behind the separation mechanism, a transmission mechanism driving the pickup mechanism, the conveying mechanism, the separation mechanism and the feeding mechanism, and an ultrasonic circuit unit disposed between the separation mechanism and the transmission mechanism. The ultrasonic circuit unit includes an ultrasonic detecting module, an amplifying circuit unit electrically connected with the ultrasonic detecting module, a paper density detecting unit electrically connected with the amplifying circuit unit, an analog-to-digital converter electrically connected with the paper density detecting unit, a processor electrically connected with the analog-to-digital converter, and a driving unit electrically connected with the processor and the transmission mechanism.

Abstract: An image scanning method is applied in an image scanning device which includes an input tray and a paper feeding sensor. The method detects whether there are papers on the input tray in step one. If there are papers, step two is executed. Otherwise, the method ends and an error is reported. In step two, papers are separated and fed. Whether the papers contact the paper feeding sensor is detected in step three. The method executes step four if the papers contact the paper feeding sensor, and ends the method with an error message otherwise. In step four, the method scans and detects whether an image of a fed edge of each of the papers is abnormal. If the image is abnormal, the method ends and an error is reported. Otherwise, scanning continues.

Abstract: Disclosed herein is a bispecific peptide conjugate comprising an epidermal growth factor receptor (EGFR) targeting peptide, an av?3 integrin targeting peptide, and a linker, where the linker is conjugated respectively to the EGFR targeting peptide and the av?3 integrin targeting peptide.