Patents by Inventor Chien-Jen Chen

Chien-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240398863
    Abstract: The present disclosure provides chimeric antigen receptor (CAR) for Human C-type lectin-like molecule-1 (CLL-1) comprising a polypeptide comprising: an extracellular antigen binding domain comprising an anti-CLL-1 single heavy chain variable domain (VH) and anti-CLL-1 single light chain variable domain (VL); a transmembrane domain; and an intracellular signaling domain. Immune effector cells comprising the CAR and pharmaceutical compositions based on the immune effector cells, as well as their therapeutic use in treating condition associated with CLL-1, are also disclosed.
    Type: Application
    Filed: September 14, 2023
    Publication date: December 5, 2024
    Inventors: Chien-Tsun KUAN, Kao-Jean HUANG, Shun-Jen YANG, Tsung-Han WU, Hui-Chun CHEN, Hom-Ming YEH
  • Patent number: 12160692
    Abstract: A projection apparatus, an illumination apparatus thereof, and a light source driving method thereof are provided. A control module converts a bit control signal into first light source timing signals, converts the first light source timing signals into second light source timing signals according to a lookup table, generates a driving current corresponding to each light source according to the lookup table, outputs second light source driving signals corresponding to the light sources according to the second light source timing signals. The lookup table includes a driving current ratio corresponding to the light sources. A driving module drives the light sources according to the second light source driving signals and the driving current for the light sources to have overlapping light-emitting timings.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: December 3, 2024
    Assignee: Coretronic Corporation
    Inventors: Hsin-Chang Huang, Chien-Yi Yang, Pei-Jen Liao, Yun-Shih Chen, Wei-Chih Su
  • Publication number: 20240393386
    Abstract: A method for adjusting position of probing base comprises steps of providing a probing machine comprising a probing holder, a first probing base having a first probing needle comprising a plurality of first probing bodies wherein two adjacent tips of the first probing bodies h a first pitch, and a second probing base having a second probe comprising a plurality of second probing bodies in which two adjacent tips of the second probing bodies has a second pitch, thereafter, grabbing the first probing base and connecting the first probing base to the probing holder, acquiring first image with respect to the plurality of first probing bodies through visual identification module, and finally, adjusting roll angle of probing tips of the plurality of first needle bodies according to the first image. Alternatively, the present invention further provides a probing machine using the method for testing DUTs having different pitches.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 28, 2024
    Inventors: YA-HUNG LO, CHIEN-HSUN CHEN, SHOU-JEN TSAI, FUH-CHYUN TANG
  • Publication number: 20240385111
    Abstract: A mask characterization method comprises measuring an interference signal of a reflection or transmission mask for use in lithography; and determining a quality metric for the reflection or transmission mask based on the interference signal. A mask characterization apparatus comprises a light source arranged to illuminate a reflective or transmissive mask with light whereby mask-reflected or mask-transmitted light is generated; an optical grating arranged to convert the mask-reflected or mask-transmitted light into an interference pattern; and an optical detector array arranged to generate an interference signal by measuring the interference pattern.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chien-Cheng Chen, Ping-Hsun Lin, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 12144065
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Publication number: 20240373187
    Abstract: An audio parameter optimizing method and a computing apparatus related to audio parameters. In the method, sound features of multiple sound signals are obtained. A wide dynamic range compression (WDRC) parameter corresponding to each of the sound signals is determined. Multiple data sets including the sound features and the corresponding WDRC parameters of the sound signals are created. The data sets are used to train a neural network, so as to generate a parameter inference model. The parameter inference model is configured to determine the WDRC parameter of a to-be-evaluated signal. Accordingly, a proper parameter could be provided.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 7, 2024
    Applicant: Acer Incorporated
    Inventors: Po-Jen Tu, Kai-Meng Tzeng, Jia-Ren Chang, Chien-Chung Chen, Ming-Chun Yu, Feng-Ming Liu, Hung-Lun Lu
  • Publication number: 20240363530
    Abstract: An integrated circuit includes a front-side horizontal conducting line and a front-side vertical conducting line at the front side of the substrate, a transistor in a semiconductor structure at the front side of the substrate, and a backside conducting line at a backside of the substrate. The front-side horizontal conducting line is directly connected to a first terminal of the transistor through a front-side terminal via-connector and directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. A word connection line directly is connected to a gate terminal of the transistor through a gate via-connector. The backside conducting line is directly connected to a second terminal of the transistor through a backside terminal via-connector. In the integrated circuit, a front-side fuse element is conductively connected to either the front-side vertical conducting line or the front-side horizontal conducting line.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Chien-Ying CHEN, Yen-Jen CHEN, Yao-Jen YANG, Meng-Sheng CHANG, Chia-En HUANG
  • Publication number: 20240337951
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Patent number: 12080641
    Abstract: An integrated circuit includes a transistor formed in a semiconductor structure, a front-side horizontal conducting line in a first metal layer above the semiconductor structure, and a front-side vertical conducting line in a second metal layer above the first metal layer. The front-side horizontal conducting line is directly connected to a first terminal of the transistor, and the front-side vertical conducting line is directly connected to the front-side horizontal conducting line. In the integrated circuit, a front-side fuse element is conductively connected to the front-side vertical conducting line, and a backside conducting line is directly connected to a second terminal of the transistor. A word connection line extending in the first direction is directly connected to a gate terminal of the transistor.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Ying Chen, Yen-Jen Chen, Yao-Jen Yang, Meng-Sheng Chang, Chia-En Huang
  • Publication number: 20240290771
    Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3?D3?S, L4?D4?S, and D3?D4.
    Type: Application
    Filed: May 8, 2024
    Publication date: August 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Publication number: 20240243522
    Abstract: In some examples, a connection apparatus includes a first connector assembly to engage with a second connector assembly, where the first connector assembly is included in one of a support stand and an electronic device, and the second connector assembly is included in another one of the support stand and the electronic device. The first connector assembly includes a floating connector block, an electrical contact on the floating connector block, and a biasing assembly engaged with the floating connector block to urge the floating connector block towards the second connector assembly when the second connector assembly is engaged with the first connector assembly to achieve a spring-loaded engagement of the electrical contact with an electrical contact of the second connector assembly.
    Type: Application
    Filed: May 28, 2021
    Publication date: July 18, 2024
    Inventors: Chih Jen Huang, Chien Feng Chu, Chih Chien Chen, Hai Lung Hung
  • Patent number: 12038693
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-Cheng Ho, Chen-Shao Hsu
  • Patent number: 11757344
    Abstract: The present disclosure provides a conversion circuit including a power supply module, positive and negative input terminals, positive and negative output terminals, a switch, an inductor, input and output capacitors, and a controller. The power supply module converts an AC power for providing three potentials on three power supply terminals respectively. The potential on the first power supply terminal is higher than the potential on the second power supply terminal, which is higher than the potential on the third power supply terminal. The positive and negative input terminals are electrically connected to the first and third power supply terminals respectively, and a voltage therebetween is an input voltage. The negative output terminal is electrically connected to the third power supply terminal. The controller is electrically connected to the positive input terminal, the second power supply terminal and the switch. A voltage across the controller is lower than the input voltage.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: September 12, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chien-Jen Chen, Chao-Shun Yang, Cheng-Hsun Chang
  • Publication number: 20230231463
    Abstract: The present disclosure provides a conversion circuit including a power supply module, positive and negative input terminals, positive and negative output terminals, a switch, an inductor, input and output capacitors, and a controller. The power supply module converts an AC power for providing three potentials on three power supply terminals respectively. The potential on the first power supply terminal is higher than the potential on the second power supply terminal, which is higher than the potential on the third power supply terminal. The positive and negative input terminals are electrically connected to the first and third power supply terminals respectively, and a voltage therebetween is an input voltage. The negative output terminal is electrically connected to the third power supply terminal. The controller is electrically connected to the positive input terminal, the second power supply terminal and the switch. A voltage across the controller is lower than the input voltage.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 20, 2023
    Inventors: Chien-Jen Chen, Chao-Shun Yang, Cheng-Hsun Chang
  • Patent number: 10600367
    Abstract: A method for driving a display device is provided. The display device includes a first driving circuit and a pixel array. The driving method includes the following step. In a first mode, by using the first driving circuit, a first light emission start signal is received to drive the pixel array. The first light emission start signal includes a plurality of first pulses, and duration of each of the first pulses is respectively overlapped with at least a part of a period of each of a first frame and at least one second frame. In a second mode, by using the first driving circuit, a second light emission start signal is received to drive the pixel array. The second light emission start signal includes a second pulse. Duration of the second pulse is overlapped with at least a part of a period of the first frame, and the second light emission start signal remains at a first level in a period of the at least one second frame.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 24, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chien-Jen Chen, Yi-Yo Dai, Tsang-Hong Wang
  • Patent number: 10332452
    Abstract: An OLED panel includes a data driver and an AMOLED. The data driver receives an input voltage and the data driver may generate a data output signal. The AMOLED may receive a positive supply voltage and a negative supply voltage and emit light according to the data output signal. In addition, the input voltage and the positive supply voltage are substantially the same.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 25, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Tsang-Hong Wang, Chien-Jen Chen, Chi-Fu Tsao, Yi-Yo Dai
  • Publication number: 20190180689
    Abstract: A method for driving a display device is provided. The display device includes a first driving circuit and a pixel array. The driving method includes the following step. In a first mode, by using the first driving circuit, a first light emission start signal is received to drive the pixel array. The first light emission start signal includes a plurality of first pulses, and duration of each of the first pulses is respectively overlapped with at least a part of a period of each of a first frame and at least one second frame. In a second mode, by using the first driving circuit, a second light emission start signal is received to drive the pixel array. The second light emission start signal includes a second pulse. Duration of the second pulse is overlapped with at least a part of a period of the first frame, and the second light emission start signal remains at a first level in a period of the at least one second frame.
    Type: Application
    Filed: March 19, 2018
    Publication date: June 13, 2019
    Inventors: Chien-Jen CHEN, Yi-Yo Dai, Tsang-Hong Wang
  • Publication number: 20180240406
    Abstract: An OLED panel includes a data driver and an AMOLED. The data driver receives an input voltage and the data driver may generate a data output signal. The AMOLED may receive a positive supply voltage and a negative supply voltage and emit light according to the data output signal. In addition, the input voltage and the positive supply voltage are substantially the same.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 23, 2018
    Inventors: Tsang-Hong WANG, Chien-Jen Chen, Chi-Fu Tsao, Yi-Yo Dai
  • Patent number: 9981050
    Abstract: Disclosed herein is a bispecific peptide conjugate comprising an epidermal growth factor receptor (EGFR) targeting peptide, an ?v?3 integrin targeting peptide, and a linker, where the linker is conjugated respectively to the EGFR targeting peptide and the ?v?3 integrin targeting peptide.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 29, 2018
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C.
    Inventors: Hung-Man Yu, Jyun-Hong Chen, Kun-Liang Lin, Chien-Jen Chen, Wuu-Jyh Lin
  • Patent number: 9926154
    Abstract: A paper feeding device includes a pickup mechanism, a conveying mechanism disposed behind the pickup mechanism, a separation mechanism disposed behind the conveying mechanism, a feeding mechanism disposed behind the separation mechanism, a transmission mechanism driving the pickup mechanism, the conveying mechanism, the separation mechanism and the feeding mechanism, and an ultrasonic circuit unit disposed between the separation mechanism and the transmission mechanism. The ultrasonic circuit unit includes an ultrasonic detecting module, an amplifying circuit unit electrically connected with the ultrasonic detecting module, a paper density detecting unit electrically connected with the amplifying circuit unit, an analog-to-digital converter electrically connected with the paper density detecting unit, a processor electrically connected with the analog-to-digital converter, and a driving unit electrically connected with the processor and the transmission mechanism.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: March 27, 2018
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Yuan Hao Tsai, Chien Jen Chen, Shih Wei Tseng, Yi Hong Chen