Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Abstract: A semiconductor structure includes a nucleation layer disposed on a substrate, an epitaxial growth layer disposed above the nucleation layer, and a superlattice structure disposed between the nucleation layer and the epitaxial growth layer. The superlattice structure includes a plurality of alternately stacked superlattice units, and adjacent two superlattice units include a first superlattice unit and a second superlattice unit. The first superlattice unit includes a first superlattice layer and a second superlattice layer stacked thereon, the second superlattice unit includes a third superlattice layer and a fourth superlattice layer stacked thereon, where each of the first, second, third and fourth superlattice layers includes a plurality of pairs of two sublayers with different compositions from each other.

Abstract: A high electron mobility transistor device includes a substrate, a plurality of pairs of alternating layers, at least one stress-relief layer and a gallium nitride layer. The plurality of pairs of alternating layers is disposed over the substrate, and each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped gallium nitride layer. The stress-relief layer is disposed between the pairs of alternating layers. The gallium nitride layer is disposed over the alternating layers.

Abstract: A high electron mobility transistor device includes a substrate, a plurality of pairs of alternating layers, at least one stress-relief layer and a gallium nitride layer. The plurality of pairs of alternating layers is disposed over the substrate, and each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped gallium nitride layer. The stress-relief layer is disposed between the pairs of alternating layers. The gallium nitride layer is disposed over the alternating layers.

Abstract: A high electron mobility transistor device includes a substrate, a superlattice buffer layer, a gradient buffer layer and a channel layer. The superlattice buffer layer are disposed over the substrate, wherein the superlattice buffer layer includes a plurality of sets of alternating layers, and each set of alternating layers includes at least one AlN layer and at least one AlxGa(1-x)N layer alternately arranged, wherein 0?x<1. The gradient buffer layer is disposed over the substrate, wherein the gradient buffer layer includes a plurality of AlyGa(1-y)N layers, wherein 0?y<1. The channel layer is disposed over the gradient buffer layer.

Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Abstract: A wafer carrier for processing a plurality of wafers includes a carrier body which rotatable about a central axis, and a plurality of pockets formed in the carrier body. Each of the pockets has an access opening and an inner periphery surface extending from the access opening to terminate at a floor surface. A lower periphery region of the inner periphery surface has a most distal region which is most distal from the central axis. When the carrier body is rotated about the central axis, a corresponding one of the wafers is less likely to be damaged due to a centrifugal force applied to the corresponding one of the wafers.

Abstract: A nanostructured chip includes a substrate and a nanostructured layer, wherein the substrate has a first surface and a second surface on which the nanostructured layer is formed. A method of producing the nanostructured chip includes the step of forming the nanostructured layer on the second surface of the substrate. Whereby, the nanostructured layer effectively disperses a stress to increase the flexural strength of the nanostructured chip. Therefore, during the subsequent procedures to form an epitaxial layer on the first surface, the nanostructured layer is helpful to prevent the epitaxial layer from generating cracks, and prevent the substrate from bowings, or fragments.

Abstract: A wafer carrier for processing a plurality of wafers includes a carrier body which rotatable about a central axis, and a plurality of pockets formed in the carrier body. Each of the pockets has an access opening and an inner periphery surface extending from the access opening to terminate at a floor surface. A lower periphery region of the inner periphery surface has a most distal region which is most distal from the central axis. When the carrier body is rotated about the central axis, a corresponding one of the wafers is less likely to be damaged due to a centrifugal force applied to the corresponding one of the wafers.

Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films and a plurality of second films, and the first films and the second films are alternately stacked on the initial layer. If the first films are doped films having dopants selected from a group consisting of carbon, iron, and the combination thereof, the second films do not include dopants substantially; if the second films are doped films having dopants selected from a group consisting of carbon, iron, and the combination thereof, the first films do not include dopants substantially.

Abstract: A semiconductor device includes a substrate, an initial layer, and a buffer stack structure. The initial layer is located on the substrate and includes aluminum nitride (AlN). The buffer stack structure is located on the initial layer and includes a plurality of base layers and at least one doped layer positioned between two adjacent base layers. Each of the base layers includes aluminum gallium nitride (AlGaN), and the doped layer includes AlGaN or boron aluminum gallium nitride (BAlGaN). In the buffer stack structure, concentrations of aluminum in the base layers gradually decrease, concentrations of gallium in the base layers gradually increase, the base layers do not contain carbon substantially, and dopants in the doped layer include carbon or iron.

Abstract: A nanostructured chip includes a substrate and a nanostructured layer, wherein the substrate has a first surface and a second surface on which the nanostructured layer is formed. A method of producing the nanostructured chip includes the step of forming the nanostructured layer on the second surface of the substrate. Whereby, the nanostructured layer effectively disperses a stress to increase the flexural strength of the nanostructured chip. Therefore, during the subsequent procedures to form an epitaxial layer on the first surface, the nanostructured layer is helpful to prevent the epitaxial layer from generating cracks, and prevent the substrate from bowings, or fragments.

Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.

Abstract: A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.

Abstract: A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.

Abstract: A new light emitting device is disclosed, including a polarizing surface layer, a light emitting layer which emits light at a wavelength, and a light transformation layer disposed between the light emitting layer and the reflective layer, wherein the light emitting layer is disposed between the reflective layer and the polarizing surface layer, and an optical thickness between the light emitting layer and the reflective layer is less than a value of five times of a quarter of the wavelength.

Abstract: A light emitting device and a fabricating method thereof are described. The light emitting device includes a substrate, a light emitting chip, a tubular structure, and a fluorescent conversion layer. The tubular structure is formed on a surface of the substrate. The light emitting chip is disposed on the surface of the substrate and is surrounded by the tubular structure. The fluorescent conversion layer is disposed in the tubular structure and covers the light emitting chip. A ratio of a maximal vertical thickness and a maximal horizontal thickness of the fluorescent conversion layer at the light emitting chip is between 0.1 and 10. A distance for the light ray to pass through the fluorescent conversion layer is controlled by using the tubular structure, so as to solve a problem of the conventional art that fluorescent powder coating package technique results in non-uniform color temperature of the emitted light.

Abstract: A bonding system and a bonding method for alignment are provided. An optical semiconductor includes a light source and a plurality of protruded elements on a surface thereof. A semiconductor bench includes a light receiving element and a plurality of recess elements on a surface thereof. A sidewall of the protruded elements or a sidewall of the recess elements is slanted. A first metallized layer is disposed on a bonding surface of each protruded element and a second metallized layer is disposed on a bottom surface of each recess element, wherein the first metallized layer is used for bonding with the second metallized layer.

Abstract: A showerhead integrating intake and exhaust is provided for showering a gas. The showerhead at least includes a showerhead body that has a gas-active surface and a plurality of intake bores thereon. The showerhead body further includes a central exhaust vent disposed on the gas-active surface. The central exhaust vent may exhaust standing gas and further pre-exhaust byproduct from reaction process.

Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.