Patents by Inventor Chien-Jung Wang

Chien-Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8729705
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Publication number: 20140103496
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Patent number: 8674508
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Publication number: 20130316073
    Abstract: A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Application
    Filed: July 29, 2013
    Publication date: November 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Patent number: 8513115
    Abstract: A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 20, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Publication number: 20130127016
    Abstract: A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.
    Type: Application
    Filed: January 18, 2013
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan WANG, Jian-Hong LIN, Chien-Jung WANG
  • Patent number: 8379365
    Abstract: A capacitor includes the first electrode including the first conductive lines and vias. The first conductive lines on the same layer are parallel to each other and connected to a first periphery conductive line. The first conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes a second electrode aligned opposite to the first electrode including second conductive lines and vias. The second conductive lines on the same layer are parallel to each other and connected to a second periphery conductive line. The second conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes oxide layers formed between the first electrode and the second electrode. The vias have rectangular (slot) shapes on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Shan Wang, Jian-Hong Lin, Chien-Jung Wang
  • Publication number: 20120263868
    Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 18, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chien-Jung Wang
  • Patent number: 8227923
    Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: July 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Publication number: 20110285031
    Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Patent number: 8013451
    Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: September 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Publication number: 20110108945
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Application
    Filed: January 17, 2011
    Publication date: May 12, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Patent number: 7893459
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Patent number: 7851793
    Abstract: A test structure includes a time dependent dielectric breakdown (TDDB) test pattern formed in a dielectric material on a wafer. The test pattern includes first and second conductive lines formed in the dielectric material. The second conductive line is adjacent to the first conductive line. The first conductive line and the second conductive line are separated by a first minimum distance at a first portion of the TDDB test pattern. The first conductive line and the second conductive line are separated by a second minimum distance at a second portion of the TDDB test pattern. The second minimum distance is greater than the first minimum distance. The second portion is different than the first portion. It also may have a third different portion with a third larger minimum distance between the first and second conductive lines. The TDDB test pattern may have a comb-comb or a comb-serpent structure, for example.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: December 14, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Ming-Zong Lin
  • Publication number: 20100271753
    Abstract: A capacitor includes the first electrode comprising the first conductive lines and vias, where the first conductive lines on the same layer are parallel to each other and connected to the first periphery conductive line, and the first conductor lines aligned in adjacent layers are coupled to each other by the vias; the second electrode aligned opposite to the first electrode comprising the second conductive lines and vias, where the second conductive lines on the same layer are parallel to each other and connected to the second periphery conductive line, and the second conductor lines aligned in adjacent layers are coupled to each other by the vias; and oxide layers formed between the first electrode and the second electrode, where the vias have rectangular (slot) shape on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten. The vias can have various sizes.
    Type: Application
    Filed: April 27, 2010
    Publication date: October 28, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan WANG, Jian-Hong LIN, Chien-Jung WANG
  • Patent number: 7646207
    Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: January 12, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
  • Publication number: 20090134526
    Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Application
    Filed: January 30, 2009
    Publication date: May 28, 2009
    Inventor: Chien-Jung Wang
  • Patent number: 7504731
    Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: March 17, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Publication number: 20090058434
    Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 5, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
  • Patent number: 7485912
    Abstract: A flexible scheme for forming a multi-layer capacitor structure is provided. The multi-layer capacitor structure includes a first electrode and a second electrode extending through at least one metallization layer, wherein the first electrode and the second electrode are separated by dielectric materials. In each of the metallization layers, the first electrode comprises a first bus and first fingers connected to the first bus, wherein the first bus comprises a first leg in a first direction, and wherein the first fingers are parallel to each other and are in a second direction. The first direction and the second direction form an acute angle. In each of the metallization layers, the second electrode comprises a second bus and second fingers connected to the second bus, wherein the second fingers are parallel to the first fingers in a same metallization layer.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: February 3, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang