Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate having a plurality of protrusions projecting from the substrate; forming a silicon layer over the substrate and each protrusion; performing an anisotropic etching to transfer the silicon layer into a silicon spacer positioned on a side wall of each protrusion; forming an oxide layer over the silicon spacer; and etching the substrate to form a recess on the substrate by using the oxide layer as a mask.

Abstract: A semiconductor device and fabrication method thereof is disclosed. The method includes the steps of providing a substrate with a trench and a stacked layer thereon, performing an epitaxy process to form an epitaxial layer in the trench, conformably depositing an oxide layer on the epitaxial layer, and removing a portion of the oxide layer and the epitaxial layer on the bottom of the trench.

Abstract: A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate having a plurality of protrusions projecting from the substrate; forming a silicon layer over the substrate and each protrusion; performing an anisotropic etching to transfer the silicon layer into a silicon spacer positioned on a side wall of each protrusion; forming an oxide layer over the silicon spacer; and etching the substrate to form a recess on the substrate by using the oxide layer as a mask.

Abstract: A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

Abstract: A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

Abstract: This ion implantation method reduces the observed levels of cross-contamination and reduces the level of variations in surface conductivity related to the provision of multiple ion implantations into a semiconductor wafer. Reduced levels of cross-contamination are obtained by purging the implantation chamber and then evacuating the implantation chamber before beginning an implantation process. This purge and evacuation cycle is believed to be particularly effective in reducing cross-contamination when two implantations are made consecutively into a wafer without removing the wafer from the implantation chamber or when successive wafers are transported into the ion implantation chamber and implantations are made into each successive wafer.