Patents by Inventor Chien-Kai Kao

Chien-Kai Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CLOCK AND DATA RECOVERY CIRCUIT USING NEURAL NETWORK CIRCUIT TO OBTAIN FREQUENCY DIFFERENCE INFORMATION
    Publication number: 20240007110
    Abstract: The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.
    Type: Application
    Filed: January 30, 2023
    Publication date: January 4, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh
  • Clock and data recovery and associated signal processing method
    Patent number: 11349485
    Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 31, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chien-Kai Kao, Tse-Hsien Yeh, Shih-Che Hung
  • CLOCK AND DATA RECOVERY AND ASSOCIATED SIGNAL PROCESSING METHOD
    Publication number: 20200244272
    Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 30, 2020
    Inventors: Chien-Kai Kao, Tse-Hsien Yeh, Shih-Che Hung