Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.

Abstract: An integrated heat dissipating assembly includes two heat sinks, a heat dissipating fan mounted between the two sinks and a body provided below the two heat sinks and the heat dissipating fan. The body is composed of a hollow body, a pump received inside the hollow body and a base attached to a bottom face of the hollow body for conducting heat from a heat source. The hollow body is divided into receiving spaces respectively communicating with water channels of the two heat sinks such that cooling water flowing inside the hollow body and the water channels of the two heat sinks is able to take away heat from the base. The heat is then dissipated by cool air due to the heat dissipating fan.

Abstract: A heat dissipator fastening kit includes two retaining bars, at least one and as many as three different brackets and multiple fasteners. The retaining bars are resilient, attach to opposite sides of an appropriate heat dissipator and respectively have two ends. The bracket attaches to a motherboard around a CPU and to the retaining bars and has several embodiments to accommodate different types of CPUs, e.g. AM2, K8, LGA775 or P4, and their motherboards. The fasteners attach the retaining bars to a heat dissipator and the bracket and the bracket to a motherboard. With such an arrangement, the heat dissipator fastening kit will be convenient and easy to use.

Abstract: An integrated heat dissipating assembly includes two heat sinks, a heat dissipating fan mounted between the two sinks and a body provided below the two heat sinks and the heat dissipating fan. The body is composed of a hollow body, a pump received inside the hollow body and a base attached to a bottom face of the hollow body for conducting heat from a heat source. The hollow body is divided into receiving spaces respectively communicating with water channels of the two heat sinks such that cooling water flowing inside the hollow body and the water channels of the two heat sinks is able to take away heat from the base. The heat is then dissipated by cool air due to the heat dissipating fan.