Patents by Inventor Chien-Kai Peng

Chien-Kai Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solar cell
    Patent number: 10312384
    Abstract: A solar cell is provided. The solar cell includes a Si substrate having a first surface and a second surface opposite to each other, an emitter, a first electrode, a doped region, a passivation layer, a doped polysilicon layer, a semiconductor layer, and a second electrode. The emitter is disposed on the first surface. The first electrode is disposed on the emitter. The doped region is disposed in the second surface. The passivation layer is disposed on the second surface. The doped polysilicon layer is disposed on the passivation layer, wherein a plurality of holes penetrates the doped polysilicon layer and the passivation layer and exposes a portion of the second surface. The semiconductor layer is disposed on the doped polysilicon layer and in the holes. The band gap of the semiconductor layer is greater than that of the Si substrate. The second electrode is disposed on the semiconductor layer.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 4, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Cheng Lin, Chien-Kai Peng, Chen-Cheng Lin, Chen-Hsun Du, Chorng-Jye Huang, Chun-Ming Yeh
  • SOLAR CELL
    Publication number: 20180114871
    Abstract: A solar cell is provided. The solar cell includes a Si substrate having a first surface and a second surface opposite to each other, an emitter, a first electrode, a doped region, a passivation layer, a doped polysilicon layer, a semiconductor layer, and a second electrode. The emitter is disposed on the first surface. The first electrode is disposed on the emitter. The doped region is disposed in the second surface. The passivation layer is disposed on the second surface. The doped polysilicon layer is disposed on the passivation layer, wherein a plurality of holes penetrates the doped polysilicon layer and the passivation layer and exposes a portion of the second surface. The semiconductor layer is disposed on the doped polysilicon layer and in the holes. The band gap of the semiconductor layer is greater than that of the Si substrate. The second electrode is disposed on the semiconductor layer.
    Type: Application
    Filed: November 15, 2016
    Publication date: April 26, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Chao-Cheng Lin, Chien-Kai Peng, Chen-Cheng Lin, Chen-Hsun Du, Chorng-Jye Huang, Chun-Ming Yeh