Patents by Inventor Chien-Kang Kao

Chien-Kang Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170032967
    Abstract: A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such as xenon and hydrogen, which are each provided at controlled volumetric ratios to ensure optimal carbon ion implantation performance. The composition can be packaged as a dopant gas kit consisting of a CO-containing supply source and a diluent mixture supply source. Alternatively, the composition can be pre-mixed and introduced from a single source that can be actuated in response to a sub-atmospheric condition achieved along the discharge flow path to allow a controlled flow of the dopant mixture from the interior volume of the device into an ion source apparatus.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Ashwini K. Sinha, Douglas C. Heiderman, Lloyd A. Brown, Serge M. Campeau, Robert Shih, Dragon Lu, Wen-Pin Chiu, Chien-Kang Kao
  • Patent number: 9552990
    Abstract: A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such as xenon and hydrogen, which are each provided at controlled volumetric ratios to ensure optimal carbon ion implantation performance. The composition can be packaged as a dopant gas kit consisting of a CO-containing supply source and a diluent mixture supply source. Alternatively, the composition can be pre-mixed and introduced from a single source that can be actuated in response to a sub-atmospheric condition achieved along the discharge flow path to allow a controlled flow of the dopant mixture from the interior volume of the device into an ion source apparatus.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 24, 2017
    Assignee: PRAXAIR TECHNOLOGY, INC.
    Inventors: Ashwini K. Sinha, Douglas C. Heiderman, Lloyd A. Brown, Serge M. Campeau, Robert Shih, Dragon Lu, Wen-Pin Chiu, Chien-Kang Kao
  • Publication number: 20140179090
    Abstract: A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such as xenon and hydrogen, which are each provided at controlled volumetric ratios to ensure optimal carbon ion implantation performance. The composition can be packaged as a dopant gas kit consisting of a CO-containing supply source and a diluent mixture supply source. Alternatively, the composition can be pre-mixed and introduced from a single source that can be actuated in response to a sub-atmospheric condition achieved along the discharge flow path to allow a controlled flow of the dopant mixture from the interior volume of the device into an ion source apparatus.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 26, 2014
    Inventors: Ashwini K. Sinha, Douglas C. Heiderman, Lloyd A. Brown, Serge M. Campeau, Robert Shih, Dragon Lu, Wen-Pin Chiu, Chien-Kang Kao
  • Publication number: 20080121984
    Abstract: A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier-trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. The concave structure comprises two grooves having a U-shaped or V-shaped profile. The grooves have an inclined plane with (111) orientation and a bottom plane with (100) orientation of the silicon substrate. The carrier-trapping region comprises a dielectric stack positioned in the concave structure, wherein the dielectric stack comprises a first oxide layer positioned on the surface of the silicon substrate, a nitride block positioned on the surface of the first oxide layer and in the concave structure, and a second oxide layer covering the first oxide layer and the nitride block.
    Type: Application
    Filed: January 30, 2008
    Publication date: May 29, 2008
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: Jason Chen, Chien Kang Kao
  • Publication number: 20070249121
    Abstract: A method of fabricating a non-volatile memory is provided. The method includes providing a substrate. Next, a tunneling oxide layer is formed on the substrate and a surface nitridation process is performed to nitridize the upper surface of the tunneling oxide layer. A plurality of nanocrystals is formed on the nitridized surface of the tunneling oxide layer. Next, the surfaces of the nanocrystals are nitridized. An oxide layer and a conductive layer are formed in sequence over the tunneling oxide layer to cover the nanocrystals. Due to the formation of high-density nanocrystals as a charge storage medium, the properties of the memory are enhanced.
    Type: Application
    Filed: July 13, 2006
    Publication date: October 25, 2007
    Inventors: Chien-Kang Kao, Chia-Ming Kuo, Chia-Lin Ku
  • Patent number: 7223658
    Abstract: A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having trapping sites interposed therein positioned on the V-groove, and a conductive layer positioned on the surface of the dielectric stack above the V-groove. A method for forming the V-groove comprises steps of forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, etching a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 29, 2007
    Assignee: Promos Technologies, Inc.
    Inventors: Jason Chen, Chien Kang Kao
  • Publication number: 20070075358
    Abstract: A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. The concave structure comprises two grooves having a U-shaped or V-shaped profile. The grooves have an inclined plane with (111) orientation and a bottom plane with (100) orientation of the silicon substrate. The carrier trapping region comprises a dielectric stack positioned in the concave structure, wherein the dielectric stack comprises a first oxide layer positioned on the surface of the silicon substrate, a nitride block positioned on the surface of the first oxide layer and in the concave structure, and a second oxide layer covering the first oxide layer and the nitride block.
    Type: Application
    Filed: November 29, 2005
    Publication date: April 5, 2007
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: Jason Chen, Chien Kang Kao
  • Patent number: 6391515
    Abstract: This invention discloses a manufacturing process for preparing sol-gel optical waveguides comprising the steps of solution preparation, an optical waveguide photoresist module process, and optical waveguide molding and sintering. The solution is prepared by mixing water and alcohol to form an alcoholic solution with a properly adjusted pH value followed by mingling with tetraethylorthosilicate (TEOS) at room temperature. The optical waveguide photoresist module process comprises the steps of soft baking, exposure, development, washing by deionized water, drying by a nitrogen gun, and hard baking. The optical waveguide molding and sintering comprises the steps of spinning, sintering, and photoresist module removal.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: May 21, 2002
    Assignees: Industrial Technology Research Institute, National Tsing Hua University
    Inventors: Jung-Chieh Su, Chien-Kang Kao, I-Nan Lin, Chuen-Horng Tsai, Cheng-Chung Chi, Yung-Sheng Liu