Patents by Inventor Chien-Kee Pang
Chien-Kee Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230411343Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.Type: ApplicationFiled: August 8, 2022Publication date: December 21, 2023Applicant: United Microelectronics Corp.Inventors: Sheng Zhang, Kai Zhu, Chien-Kee Pang, Chia-Liang Liao
-
Publication number: 20230154926Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.Type: ApplicationFiled: January 11, 2023Publication date: May 18, 2023Inventors: Sheng Zhang, Chunyuan QI, Xingxing Chen, Chien-Kee Pang
-
Publication number: 20230094739Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.Type: ApplicationFiled: October 26, 2021Publication date: March 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: CHUNYUAN QI, Sheng Zhang, XINGXING CHEN, Chien-Kee Pang
-
Patent number: 11605648Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.Type: GrantFiled: July 22, 2021Date of Patent: March 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang
-
Publication number: 20220415926Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.Type: ApplicationFiled: July 22, 2021Publication date: December 29, 2022Applicant: United Microelectronics Corp.Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang
-
Publication number: 20220399239Abstract: A chips bonding auxiliary structure includes a first chip, an auxiliary pattern and a second chip. The first chip has a first surface. The auxiliary pattern is form on the first surface. The second chip has a second surface bonding to the first surface to form at least one gap space surrounding the auxiliary pattern.Type: ApplicationFiled: August 22, 2022Publication date: December 15, 2022Inventors: Sheng ZHANG, Chien-Kee PANG, Xin ZHAO
-
Patent number: 11456221Abstract: A method for measuring chips bonding strength includes steps as follows: An auxiliary pattern is formed on a first surface of a first chip. A second surface of a second chip is bonded to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, dimensions of the at least one gap space and the auxiliary pattern are measure respectively; and the bonding strength between the first chip and the second chip is estimated according to the dimensions.Type: GrantFiled: June 19, 2020Date of Patent: September 27, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng Zhang, Chien-Kee Pang, Xin Zhao
-
Publication number: 20210358818Abstract: A method for measuring chips bonding strength includes steps as follows: An auxiliary pattern is formed on a first surface of a first chip. A second surface of a second chip is bonded to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, dimensions of the at least one gap space and the auxiliary pattern are measure respectively; and the bonding strength between the first chip and the second chip is estimated according to the dimensions.Type: ApplicationFiled: June 19, 2020Publication date: November 18, 2021Inventors: Sheng ZHANG, Chien-Kee PANG, Xin ZHAO
-
Patent number: 10622253Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.Type: GrantFiled: June 12, 2018Date of Patent: April 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
-
Patent number: 10580823Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.Type: GrantFiled: May 3, 2017Date of Patent: March 3, 2020Assignee: United Microelectronics Corp.Inventors: Sheng Zhang, Wen-Bo Ding, Zhi-Rui Sheng, Chien-En Hsu, Chien-Kee Pang
-
Publication number: 20190378757Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Applicant: United Microelectronics Corp.Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
-
Publication number: 20180323227Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Applicant: United Microelectronics Corp.Inventors: Sheng Zhang, Wen-Bo Ding, Zhi-Rui Sheng, Chien-En Hsu, Chien-Kee Pang
-
Patent number: 9852912Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.Type: GrantFiled: September 20, 2016Date of Patent: December 26, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng Zhang, Liang Yi, Wen-Bo Ding, Chien-Kee Pang, Yu-Yang Chen
-
Patent number: 9780101Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.Type: GrantFiled: November 24, 2016Date of Patent: October 3, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng Zhang, Wenbo Ding, Xiaofei Han, Chien-Kee Pang, Yu-Yang Chen, Jubao Zhang
-
Publication number: 20080200039Abstract: The invention is directed to a nitridation process for a wafer. The nitridation process comprises steps of disposing the wafer on a top surface of a chuck in a nitridation process tool, wherein a plurality of concentric pipe coils is disposed close to the bottom surface of the chuck. Then, the chuck is heated and the chuck is regionally cooling down by applying a coolant into the concentric pipe coils, wherein the flow rates of the coolant in the concentric pipe coils are different from each other. Furthermore, a plasma nitridation process is performed on the wafer.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wenshen Li, Chien-Kee Pang, Ching-Yang Wen, Teng-Ming Hoong