Patents by Inventor Chien-Ko Liao

Chien-Ko Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210063984
    Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
  • Publication number: 20210065347
    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Chien-Ko LIAO, Ya-Hsun HSUEH, Sheng-Hsiang CHUANG, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
  • Patent number: 10872794
    Abstract: A system and method for inline detection of defects on a semiconductor wafer surface during a semiconductor device manufacturing process is disclosed herein. In one embodiment, a method includes: automatically transporting the wafer from a first processing station to an inspection station; scanning a wafer surface using a camera in the inspection station; generating at least one image of the wafer surface; analyzing the at least one image to detect defects on the wafer surface based on a set of predetermined criteria; if the wafer is determined to be defective, automatically transporting the wafer from the inspection station to a stocker; and if the wafer is determined to be not defective, automatically transporting the wafer to a second processing station for further processing in accordance with the semiconductor device manufacturing process.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ko Liao, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Ya Hsun Hsueh
  • Patent number: 10852704
    Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
  • Patent number: 10839507
    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Publication number: 20200043812
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Patent number: 10490463
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20190163149
    Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.
    Type: Application
    Filed: July 6, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
  • Publication number: 20190164265
    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
    Type: Application
    Filed: August 21, 2018
    Publication date: May 30, 2019
    Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shul Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Publication number: 20190035696
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Application
    Filed: February 26, 2018
    Publication date: January 31, 2019
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20180366357
    Abstract: A system and method for inline detection of defects on a semiconductor wafer surface during a semiconductor device manufacturing process is disclosed herein. In one embodiment, a method includes: automatically transporting the wafer from a first processing station to an inspection station; scanning a wafer surface using a camera in the inspection station; generating at least one image of the wafer surface; analyzing the at least one image to detect defects on the wafer surface based on a set of predetermined criteria; if the wafer is determined to be defective, automatically transporting the wafer from the inspection station to a stocker; and if the wafer is determined to be not defective, automatically transporting the wafer to a second processing station for further processing in accordance with the semiconductor device manufacturing process.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 20, 2018
    Inventors: Chien-Ko LIAO, Hsu-Shui LIU, Jiun-Rong PAI, Sheng-Hsiang CHUANG, Shou-Wen KUO, Ya Hsun HSUEH
  • Patent number: 9811000
    Abstract: A photolithography tool includes at least one process chamber, at least one front opening unified pod (FOUP) stage, at least one moving mechanism, and an image sensor. The moving mechanism is configured to move the wafer from the process chamber to the FOUP stage. The image sensor is configured to capture the image of the wafer on the moving mechanism.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Feng Liao, Chun-Hsien Lin, Pei-Yi Su, Yi-Ming Dai, Chung-Hsing Lee, Chien-Ko Liao, Chun-Yung Chang, Nan-Jung Chen, Pei-Yuan Wu, Hsien-Mao Huang
  • Publication number: 20170123328
    Abstract: A photolithography tool includes at least one process chamber, at least one front opening unified pod (FOUP) stage, at least one moving mechanism, and an image sensor. The moving mechanism is configured to move the wafer from the process chamber to the FOUP stage. The image sensor is configured to capture the image of the wafer on the moving mechanism.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Chia-Feng LIAO, Chun-Hsien LIN, Pei-Yi SU, Yi-Ming DAI, Chung-Hsing LEE, Chien-Ko LIAO, Chun-Yung CHANG, Nan-Jung CHEN, Pei-Yuan WU, Hsien-Mao HUANG
  • Patent number: 9553073
    Abstract: A chip stack structure using conductive film bridge adhesive technology comprises a substrate, a first chip, at least one bridge element, a conductive film, and a second chip. The first chip is electrically connected to a first electrode of the substrate. The at least one bridge element has a first bridge surface and a second bridge surface at two ends, and the first bridge surface and the second bridge surface are electrically connected to the first chip and a second electrode of the substrate, respectively. The conductive film is electrically connected to the first bridge surface of the at least one bridge element. The second chip is stacked and electrically connected to the conductive film. Thus, the structure of the present invention not only facilitates the ease of stacking the chips but also increases the effectiveness of the chips heat dissipation and ability of withstanding electrical current.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: January 24, 2017
    Assignee: LINGSEN PRECISION INDUSTRIES, LTD
    Inventors: Chien-Ko Liao, Tzu-Chih Lin
  • Publication number: 20150255423
    Abstract: A copper clad laminate is disclosed to include a substrate defining a plurality of carrier zones for attachment of chips and having a plurality of barrier portions each arranged around at least one of the carrier zones for isolating the carrier zones. Thus, when tin sheets mounted between the chips and the carrier zones of the substrate become liquids in a thermal reflow process, the barrier portions of the substrate will stop an overflow of molten tin to prevent the chips from damage caused by a solder bridge problem.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 10, 2015
    Inventors: Tzu-Chih LIN, Chien-Ko LIAO
  • Publication number: 20150206852
    Abstract: A copper clad laminate is disclosed to include a substrate defining a plurality of carrier zones for attachment of chips and having a plurality of barrier portions each arranged around at least one of the carrier zones for isolating the carrier zones. Thus, when tin sheets mounted between the chips and the carrier zones of the substrate become liquids in a thermal reflow process, the barrier portions of the substrate will stop an overflow of molten tin to prevent the chips from damage caused by a solder bridge problem.
    Type: Application
    Filed: April 25, 2014
    Publication date: July 23, 2015
    Applicant: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Tzu-Chih LIN, Chien-Ko LIAO
  • Publication number: 20150187735
    Abstract: A chip stack structure using conductive film bridge adhesive technology comprises a substrate, a first chip, at least one bridge element, a conductive film, and a second chip. The first chip is electrically connected to a first electrode of the substrate. The at least one bridge element has a first bridge surface and a second bridge surface at two ends, and the first bridge surface and the second bridge surface are electrically connected to the first chip and a second electrode of the substrate, respectively. The conductive film is electrically connected to the first bridge surface of the at least one bridge element. The second chip is stacked and electrically connected to the conductive film. Thus, the structure of the present invention not only facilitates the ease of stacking the chips but also increases the effectiveness of the chips heat dissipation and ability of withstanding electrical current.
    Type: Application
    Filed: April 18, 2014
    Publication date: July 2, 2015
    Applicant: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Chien-Ko LIAO, Tzu-Chih LIN
  • Publication number: 20150185148
    Abstract: A gas sensor having a micro-package structure includes a light-emitting unit, a light-receiving unit, and a signal-processing unit all deposited on a substrate, and a package body fixed to the substrate and having a chamber and a through hole. The chamber accommodates all the units and the through hole is over the substrate. Gas enters the chamber through the through hole. The light-emitting unit emits an optical signal that passes through the gas and then is received by the light-receiving unit. Then a signal-processing unit electrically connected to the light-receiving unit performs spectral analysis. Thereby, the gas sensor is advantageous for requiring low packaging costs and being compact.
    Type: Application
    Filed: February 3, 2014
    Publication date: July 2, 2015
    Applicant: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Tzu-Chih LIN, Chien-Ko LIAO
  • Patent number: 9063084
    Abstract: A gas sensor having a micro-package structure includes a light-emitting unit, a light-receiving unit, and a signal-processing unit all deposited on a substrate, and a package body fixed to the substrate and having a chamber and a through hole. The chamber accommodates all the units and the through hole is over the substrate. Gas enters the chamber through the through hole. The light-emitting unit emits an optical signal that passes through the gas and then is received by the light-receiving unit. Then a signal-processing unit electrically connected to the light-receiving unit performs spectral analysis. Thereby, the gas sensor is advantageous for requiring low packaging costs and being compact.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: June 23, 2015
    Assignee: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Tzu-Chih Lin, Chien-Ko Liao
  • Patent number: 8212360
    Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: July 3, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Chien-Ko Liao, Chin-Tien Chiu, Jack Chang Chien, Cheemen Yu, Hem Takiar