Abstract: A method for data transmission in a device coupled to a host via a bus is provided. A sequence of data packets are received from the host and the received data packets are stored into a buffering unit of the device. It is then determined whether a predetermined error has occurred. When the predetermined error has occurred, the buffering unit of the device is locked to stop receiving the data packets. Thereafter, the buffering unit of the device is unlocked according to an unlock request from the host to resume receiving subsequent data packets.

Abstract: In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.

Abstract: In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.

Abstract: A method for data transmission in a device coupled to a host via a bus is provided. A sequence of data packets are received from the host and the received data packets are stored into a buffering unit of the device. It is then determined whether a predetermined error has occurred. When the predetermined error has occurred, the buffering unit of the device is locked to stop receiving the data packets. Thereafter, the buffering unit of the device is unlocked according to an unlock request from the host to resume receiving subsequent data packets.

Abstract: In a host-slave data transfer system, the slave device transmits data regarding its status and buffer conditions to the host using tailers inserted into the data being transferred to the host. The slave device has a plurality of buffers, a buffer management circuit which manages the buffers and obtains buffer condition information (e.g. amount of available buffer space, amount of buffered data to be transferred to the host), a detection circuit which collects interrupt status of the slave, a processing circuit which generates headers or tailers containing the buffer conditions information and interrupt status, and a merging circuit which merges multiple data segments received from the data-source/data-destination device and associated headers and tailers to generate a stream of merged data. The host obtains the buffer condition information from the tailers, and uses it to determine the amount of data to transmit or receive from the slave.

Abstract: A method of accessing internal memory of a processor and the device thereof. The method employs a bank swapping mechanism for the processing unit of a processor and a direct memory access controller to simultaneously access different memory units in internal memory. The processing unit can continuously access and process data in the internal memory to optimize its efficiency. In the device, the processing unit of a processor and a direct memory access controller are coupled to internal memory through a switching circuit, the switch of which enables the processing unit and the direct memory access controller to access different memory units in the internal memory. Therefore, the processing unit can continuously access and process data in the internal memory to optimize its efficiency.

Abstract: A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outputting an at-speed clock signal. The frequency of the at-speed clock signal is substantially the same with that of the reference clock signal. The multiplexer is for receiving the at-speed clock signal and a scan chain clock signal and outputting a test clock signal according to the scan chain enable signal. The frequency of the reference clock signal is higher than that of the scan chain clock.

Abstract: A method of accessing internal memory of a processor and the device thereof. The method employs a bank swapping mechanism for the processing unit of a processor and a direct memory access controller to simultaneously access different memory units in internal memory. The processing unit can continuously access and process data in the internal memory to optimize its efficiency. In the device, the processing unit of a processor and a direct memory access controller are coupled to internal memory through a switching circuit, the switch of which enables the processing unit and the direct memory access controller to access different memory units in the internal memory. Therefore, the processing unit can continuously access and process data in the internal memory to optimize its efficiency.

Abstract: A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outputting an at-speed clock signal. The frequency of the at-speed clock signal is substantially the same with that of the reference clock signal. The multiplexer is for receiving the at-speed clock signal and a scan chain clock signal and outputting a test clock signal according to the scan chain enable signal. The frequency of the reference clock signal is higher than that of the scan chain clock.