Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.

Abstract: A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.

Abstract: A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.

Abstract: A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level.

Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.

Abstract: A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.

Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.