Patents by Inventor Chien-Kwen CHEN

Chien-Kwen CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Overlay structure and method of fabricating the same
    Patent number: 10790205
    Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Pin Chen, Te-Chia Ku, Chien-Kwen Chen, Chi-Chang Wu, Cheng-Ming Ho
  • OVERLAY STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20200105629
    Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.
    Type: Application
    Filed: January 10, 2019
    Publication date: April 2, 2020
    Inventors: Feng-Pin CHEN, Te-Chia KU, Chien-Kwen CHEN, Chi-Chang WU, Cheng-Ming HO