Patents by Inventor Chien-Liang Tung

Chien-Liang Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8278709
    Abstract: A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: October 2, 2012
    Assignee: Himax Technologies Limited
    Inventors: Chun-Yu Chou, Chien-Liang Tung, Chi-Wei Lin
  • Publication number: 20120080752
    Abstract: A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Inventors: Chun-Yu Chou, Chien-Liang Tung, Chi-Wei Lin
  • Publication number: 20110195553
    Abstract: A method of fabricating a semiconductor device is provided. The method comprises: forming a first layer; forming a P-well on the first layer; forming an isolation region in the P-well; performing an extra implantation on a surface between the P-well and the first layer; and forming a source/drain region. The method of the present invention can solve the punch through problem of the conventional iso-NMOS transistor without increasing cost.
    Type: Application
    Filed: February 8, 2010
    Publication date: August 11, 2011
    Inventors: Chun-Yu Chou, Chien-Liang Tung, Chi-Wei Lin