Patents by Inventor Chien-Liang Wu
Chien-Liang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973133Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.Type: GrantFiled: May 8, 2023Date of Patent: April 30, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Patent number: 11937932Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: GrantFiled: July 8, 2022Date of Patent: March 26, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
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Publication number: 20240090234Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
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Patent number: 11864391Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).Type: GrantFiled: December 26, 2022Date of Patent: January 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
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Patent number: 11854632Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.Type: GrantFiled: October 15, 2021Date of Patent: December 26, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chien-Liang Wu, Wen-Kai Lin, Te-Wei Yeh, Sheng-Yuan Hsueh, Chi-Horn Pai
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Publication number: 20230380148Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.Type: ApplicationFiled: June 20, 2022Publication date: November 23, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Kai Kang, Ting-Hsiang Huang, Chien-Liang Wu, Sheng-Yuan Hsueh, Chi-Horn Pai
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Patent number: 11765891Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.Type: GrantFiled: August 2, 2021Date of Patent: September 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chun-Hsien Lin, Yung-Chen Chiu, Chien-Liang Wu, Te-Wei Yeh
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Publication number: 20230275146Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20230275147Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Patent number: 11705512Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).Type: GrantFiled: February 21, 2022Date of Patent: July 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Yi-Chung Sheng, Sheng-Yuan Hsueh, Chih-Kai Kang, Guan-Kai Huang, Chien-Liang Wu
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Publication number: 20230223400Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Te-Wei Yeh, Yi-Chun Chen
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Publication number: 20230223399Abstract: A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Te-Wei Yeh, Yi-Chun Chen
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Patent number: 11688800Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.Type: GrantFiled: August 16, 2020Date of Patent: June 27, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Kuo-Yu Liao
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Publication number: 20230147512Abstract: An OTP memory capacitor structure includes a semiconductor substrate, a bottom electrode, a capacitor insulating layer and a metal electrode stack structure. The bottom electrode is provided on the semiconductor substrate. The capacitor insulating layer is provided on the bottom electrode. The metal electrode stack structure includes a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence. The metal layer is provided on the capacitor insulating layer and is used as a top electrode. The insulating sacrificial layer is provided between the metal layer and the capping layer. A manufacturing method of the OTP memory capacitor structure is also provided. By the provision of the insulating sacrificial layer, the bottom electrode formed first can be prevented from being damaged by subsequent etching and other processes, so that the OTP memory capacitor structure has better electrical characteristics.Type: ApplicationFiled: December 7, 2021Publication date: May 11, 2023Inventors: KUO-HSING LEE, Po-Wen Su, Chien-Liang Wu, Sheng-Yuan Hsueh
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Publication number: 20230135847Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).Type: ApplicationFiled: December 26, 2022Publication date: May 4, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
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Patent number: 11631761Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).Type: GrantFiled: February 22, 2022Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Yi-Chung Sheng, Sheng-Yuan Hsueh, Chih-Kai Kang, Guan-Kai Huang, Chien-Liang Wu
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Patent number: 11631664Abstract: A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.Type: GrantFiled: October 21, 2020Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Te-Wei Yeh, Yi-Chun Chen
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Publication number: 20230081533Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.Type: ApplicationFiled: October 15, 2021Publication date: March 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chien-Liang Wu, Wen-Kai Lin, Te-Wei Yeh, Sheng-Yuan Hsueh, Chi-Horn Pai
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Patent number: 11605631Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.Type: GrantFiled: November 2, 2021Date of Patent: March 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yung-Chen Chiu, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chien-Liang Wu, Chih-Kai Kang, Guan-Kai Huang
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Patent number: 11569295Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).Type: GrantFiled: July 8, 2020Date of Patent: January 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu