Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.

Abstract: An EUV lithography mask including a substrate, a patterned absorber layer including a first material and a second material. In some embodiments, the first material is a second row transition metal and the second material is a first row transition metal or second row transition metal. The disclosed EUV lithography masks reduce undesirable mask 3D effects.

Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

Abstract: Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.

Abstract: The embodiments of the disclosure provide a method for setting subband full duplex (SBFD) resource and user equipment (UE). The method includes: receiving a first configuration from a network device, wherein the first configuration indicates a plurality of transmission directions for a time period; receiving a second configuration from the network device, wherein the second configuration indicates at least one SBFD resource within the time period; and performing a communication operation with the network device according to the first configuration and the second configuration.

Abstract: A semiconductor structure includes a substrate, an isolation structure disposed in the substrate, and a hybrid structure disposed over the isolation structure. The hybrid structure is substantially conformal with respect to a profile of the isolation structure. The hybrid structure includes an oxide component, a nitride component surrounding the oxide component, and a first polysilicon component alongside the nitride component. The nitride component includes a first upper surface closed to the first polysilicon component, and a second upper surface distal to the first polysilicon component. The second upper surface is lower than the first upper surface.

Abstract: The embodiments of the disclosure provide a method for setting subband full duplex (SBFD) resource and user equipment (UE). The method includes: receiving a first configuration from a network device, wherein the first configuration indicates a plurality of first transmission directions for a time period; receiving a second configuration from the network device, wherein the second configuration indicates at least one SBFD resource within the time period; receiving a downlink control information (DCI) from the network device, wherein the DCI indicates at least one second transmission directions for at least one slot within the time period; and performing a communication operation with the network device according to the first configuration, the second configuration, and the DCI.

Abstract: The embodiments of the disclosure provide a method for setting subband full duplex (SBFD) resource and user equipment (UE). The method includes: receiving a first configuration from a network device, wherein the first configuration indicates a plurality of transmission directions for a time period; receiving a second configuration from the network device, wherein the second configuration indicates at least one SBFD resource within the time period; receiving a third configuration from the network device, wherein the third configuration indicates a downlink bandwidth part and an uplink bandwidth part; performing a communication operation with the network device according to the first configuration, the second configuration, and the third configuration.

Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.

Abstract: An attenuated phase-shifting mask (APSM) includes a substrate, a multi-layer structure, a capping layer and an absorber layer. The substrate has a first side and a second side opposite to the first side. The multi-layer structure is disposed over the first side of the substrate. The capping layer is disposed over the multi-layer structure. The absorber layer is disposed over a portion of the capping layer. The absorber layer includes a first material and a second material different from the first material. A thickness of the absorber layer is between approximately 30 nm and approximately 65 nm. A refractive index (n) of the absorber layer is between approximately 0.860 and approximately 0.945. An extinction coefficient (k) of the absorber layer is between approximately 0.070 and approximately 0.015.

Abstract: The present application discloses an adapter for data transmission between a first communication device and a second communication device, in which the first communication device reads data in the second communication device, and the data includes a plurality of data segments, wherein a size of each data segment is the maximum transmission unit of the second communication device. The adapter includes a buffer and a plurality of counters. The buffer stores the data transmitted by the second communication device temporarily. The plurality of counters are initially set to zero. Each counter corresponds to each data segment and indicates a size of partial data of each data segment that has been stored. The adapter transmits the partial data to the first communication device, when each counter indicates that the size of the partial data reaches a predetermined transmission unit but does not reach the maximum transmission unit.

Abstract: A dual drive pressing apparatus for plural pressing heads is disclosed. The dual drive pressing apparatus includes a platform, a first rotation plate, a second rotation plate, a return set and a switch set. While the first rotation plate is driven by a first driving force, the first rotation plate rotates with the second rotation plate to a selectively specific angle relative to the platform, and the set of pressing columns is selectively aligned with a corresponding pressing head. While a second driving force is provided by the switch set to resist the resilience of the return set and push against the end of the supporting cylinder to move towards the second surface, the supporting cylinder of the second rotation plate drives the fourth surface separated from the first rotation plate, and the set of pressing columns on the third surface pushes the corresponding pressing head set.

Abstract: The disclosure relates to a dual drive pressing apparatus for plural pressing heads. The dual drive pressing apparatus includes a platform, a first rotation plate, a second rotation plate, a return set and a switch set. While the first rotation plate is driven by a first driving force, the first rotation plate rotates with the second rotation plate to a selectively specific angle relative to the platform, and the set of pressing columns is selectively aligned with a corresponding pressing head. While a second driving force is provided by the switch set to resist the resilience of the return set and push against the end of the supporting cylinder to move towards the second surface, the supporting cylinder of the second rotation plate drives the fourth surface separated from the first rotation plate, and the set of pressing columns on the third surface pushes the corresponding pressing head set.

Abstract: A roller-type lateral force generation device includes a roller, a first plate, a second plate, a connection plate, a first spring, a rotation shaft, a second spring, a fixing element and an adjustment element. The connection plate is disposed along a set direction, which is perpendicular to a paper-feeding direction. The first spring is disposed between the first plate and a first shaft portion of a roller shaft of the roller. The second spring is disposed between the second plate and a second shaft portion of the roller shaft. The adjustment element has a limitation plate perpendicular to the first plate. The limitation plate has a limitation groove. The first shaft portion is penetrated through the limitation groove. The set direction and the connection line of the rotation shaft and the roller shaft have an angle larger than 0 degree. A lateral force is generated, thereby avoiding paper squeezing inward.

Abstract: A mobile device includes a processing module, an external connection interface and a current monitoring unit. The external connection interface is electrically connected to the processing module and includes a first pin, a second pin and a third pin. The first pin is configured to transmit a first speaker signal and the second pin is configured to transmit a second speaker signal. The current monitoring unit is electrically connected to the processing module and the third pin of the external connection interface and configured to monitor a current state of the third pin and feedback the monitored current state to the processing module. The processing module is configured to provide one of a plurality of different voltage levels to the third pin according to the monitored current state. A noise-canceling earphone is also disclosed.

Abstract: A mobile device includes a processing module, an external connection interface and a current monitoring unit. The external connection interface is electrically connected to the processing module and includes a first pin, a second pin and a third pin. The first pin is configured to transmit a first speaker signal and the second pin is configured to transmit a second speaker signal. The current monitoring unit is electrically connected to the processing module and the third pin of the external connection interface and configured to monitor a current state of the third pin and feedback the monitored current state to the processing module. The processing module is configured to provide one of a plurality of different voltage levels to the third pin according to the monitored current state. A noise-canceling earphone is also disclosed.

Abstract: An LED package structure includes an LED die, a lead frame and a housing connecting to the lead frame. The LED die is located on a surface of the lead frame. The housing includes an inner face surrounding the LED die. The inner face has a bottom edge connected to the surface of the lead frame, a top edge and a waist line between the bottom edge and top edge. The bottom edge surrounds an area less than an area surrounded by the waist line. The area surrounded by the waist line is less than an area surrounded by the top edge. The inner face has a curved surface between the waist line and the bottom edge.

Abstract: A semiconductor package includes at least four lead frames each having an extending portion and a connecting portion, a heat dissipation plate having a top surface and a bottom surface, at least one semiconductor chip positioned on the top surface of the heat dissipation plate. At least one conductive wire electrically connects the chip to the lead frames. An encapsulation covers the lead frames, the heat dissipation plate, the semiconductor chip, and the conductive wires, while the bottom surface of the heat dissipation plate and the extending portions of the lead frames are exposed.