Patents by Inventor Chien-Min Hsu
Chien-Min Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250139349Abstract: A multi-chip integrated package design system includes a model analysis, a 3D model analysis and an electrical simulation. The model analysis obtains a pin connection mode of the designed circuit according to a designed circuit, obtains at least one conductive layer of the designed circuit according to a layer stackup, selects a transmission line model that meets the pin connection mode and at least one conductive layer, substitutes the layer stackup and a design rule into the selected transmission line model to generate an equivalent circuit, generates a corresponding relationship according to the equivalent circuit, and obtains the transmission line length corresponding to a parameter design target according to the corresponding relationship. The 3D model analysis constructs a 3D model of the designed circuit according to the obtained the transmission line length. The electrical simulation determines whether the characteristic parameter of the 3D model meets the parameter design target.Type: ApplicationFiled: December 28, 2023Publication date: May 1, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min HSU, Chang-Tzu LIN, Shih-Hsien WU
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Patent number: 11917754Abstract: An antenna module comprises: a circuit board, having a three-dimensional keep-out area; an antenna, disposed on the circuit board and located in the keep-out area; and a metal piece, disposed on the circuit board and located in the keep-out area, wherein the metal piece is electrically insulated from the antenna.Type: GrantFiled: October 11, 2021Date of Patent: February 27, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Chien-Min Hsu
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Publication number: 20220400549Abstract: An antenna module comprises: a circuit board, having a three-dimensional keep-out area; an antenna, disposed on the circuit board and located in the keep-out area; and a metal piece, disposed on the circuit board and located in the keep-out area, wherein the metal piece is electrically insulated from the antenna.Type: ApplicationFiled: October 11, 2021Publication date: December 15, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Chien-Min HSU
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Publication number: 20220201870Abstract: A fabrication method of a flexible electronic package device including the following steps is provided. A tolerable bending radius of the flexible electronic package device is obtained. A minimum surface curvature radius of a selected portion of an applied carrier is obtained. A relationship of the tolerable bending radius being smaller than the minimum surface curvature radius is ensured. The flexible electronic package device is disposed on the selected portion.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Applicant: Industrial Technology Research InstituteInventors: Chien-Min Hsu, Chih-Ming Shen, Shih-Hsien Wu
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Patent number: 11363724Abstract: A fabrication method of a flexible electronic package device including the following steps is provided. A tolerable bending radius of the flexible electronic package device is obtained. A minimum surface curvature radius of a selected portion of an applied carrier is obtained. A relationship of the tolerable bending radius being smaller than the minimum surface curvature radius is ensured. The flexible electronic package device is disposed on the selected portion.Type: GrantFiled: December 18, 2020Date of Patent: June 14, 2022Assignee: Industrial Technology Research InstituteInventors: Chien-Min Hsu, Chih-Ming Shen, Shih-Hsien Wu
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Patent number: 11239146Abstract: A package structure is provided. The package structure includes a substrate. The package structure also includes a hybrid pad disposed on the substrate. The hybrid pad includes a metal layer and a buffer layer connected to the metal layer. The Young's modulus of the buffer layer is less than the Young's modulus of the metal layer. The package structure further includes an electrically connecting structure disposed on the hybrid pad. The package structure includes a chip layer electrically connected to the electrically connecting structure. The package structure also includes a bonding pad disposed between the electrically connecting structure and the chip layer.Type: GrantFiled: July 8, 2020Date of Patent: February 1, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min Hsu, Chih-Ming Shen
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Patent number: 11061694Abstract: A reconfigurable data bus system comprises a driver, a receiver, a data bus and a detector. The driver stores an electrical parameter data base. The electrical parameter data base includes a plurality of different signal-to-ground ratios and a plurality of signal quality parameters corresponding to the signal-to-ground ratios. The data bus includes a plurality of signal lines electrically connected between the driver and the receiver. The detector is electrically connected to the data bus and the driver. The detector is configured to detect a current signal quality parameter of the data bus and transmit the current signal quality parameter to the driver. The driver is selectively reconfigured a current signal-to-ground ratio according to a current signal quality parameter of the data bus and the electrical parameter database.Type: GrantFiled: November 7, 2019Date of Patent: July 13, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min Hsu, Shih-Hsien Wu
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Publication number: 20210202367Abstract: A package structure is provided. The package structure includes a substrate. The package structure also includes a hybrid pad disposed on the substrate. The hybrid pad includes a metal layer and a buffer layer connected to the metal layer. The Young's modulus of the buffer layer is less than the Young's modulus of the metal layer. The package structure further includes an electrically connecting structure disposed on the hybrid pad. The package structure includes a chip layer electrically connected to the electrically connecting structure. The package structure also includes a bonding pad disposed between the electrically connecting structure and the chip layer.Type: ApplicationFiled: July 8, 2020Publication date: July 1, 2021Inventors: Chien-Min HSU, Chih-Ming SHEN
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Publication number: 20200142713Abstract: A reconfigurable data bus system comprises a driver, a receiver, a data bus and a detector. The driver stores an electrical parameter data base. The electrical parameter data base includes a plurality of different signal-to-ground ratios and a plurality of signal quality parameters corresponding to the signal-to-ground ratios. The data bus includes a plurality of signal lines electrically connected between the driver and the receiver. The detector is electrically connected to the data bus and the driver. The detector is configured to detect a current signal quality parameter of the data bus and transmit the current signal quality parameter to the driver. The driver is selectively reconfigured a current signal-to-ground ratio according to a current signal quality parameter of the data bus and the electrical parameter database.Type: ApplicationFiled: November 7, 2019Publication date: May 7, 2020Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min HSU, Shih-Hsien WU
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Patent number: 10405418Abstract: A differential signal transmitting circuit board includes a substrate, at least two differential conductive elements, and at least one insulating element. The differential conductive elements are disposed in the substrate. The insulating element is disposed in the substrate. The insulating element is close to or contacted to the differential conductive elements. A material of the substrate has a first equivalent dielectric constant. A material of the insulating element has a second equivalent dielectric constant. The first equivalent dielectric constant is different from the second equivalent dielectric constant.Type: GrantFiled: December 21, 2016Date of Patent: September 3, 2019Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min Hsu, Shih-Hsien Wu
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Patent number: 10129974Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones.Type: GrantFiled: August 24, 2016Date of Patent: November 13, 2018Assignees: Industrial Technology Research Institute, First Hi-tec Enterprise Co., Ltd., NEXCOM International Co., Ltd.Inventors: Chien-Min Hsu, Min-Lin Lee, Huey-Ru Chang, Hung-I Liu, Ching-shan Chang
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Publication number: 20180177044Abstract: A differential signal transmitting circuit board includes a substrate, at least two differential conductive elements, and at least one insulating element. The differential conductive elements are disposed in the substrate. The insulating element is disposed in the substrate. The insulating element is close to or contacted to the differential conductive elements. A material of the substrate has a first equivalent dielectric constant. A material of the insulating element has a second equivalent dielectric constant. The first equivalent dielectric constant is different from the second equivalent dielectric constant.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min HSU, Shih-Hsien WU
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Publication number: 20170273174Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones.Type: ApplicationFiled: August 24, 2016Publication date: September 21, 2017Applicants: Industrial Technology Research Institute, First Hi-tec Enterprise Co.,Ltd., NEXCOM International Co., Ltd.Inventors: Chien-Min Hsu, Min-Lin Lee, Huey-Ru Chang, Hung-I Liu, Ching-shan Chang
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Patent number: 9706656Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.Type: GrantFiled: November 24, 2015Date of Patent: July 11, 2017Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min Hsu, Shih-Hsien Wu, Jing-Yao Chang, Tao-Chih Chang, Ren-Shin Cheng, Min-Lin Lee
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Patent number: 9595754Abstract: A method for forming a patterned conductive structure is provided. The method includes forming a soluble layer on a surface of a substrate, wherein the soluble layer has an opening exposing a rough portion of the surface. A first conductive layer is formed on the soluble layer, wherein the first conductive layer extends onto the rough portion in the opening. The soluble layer and the first conductive layer on the soluble layer are removed, wherein a portion of the first conductive layer corresponding to the rough portion is remained on the substrate. A patterned conductive structure formed by the method is also provided.Type: GrantFiled: December 26, 2014Date of Patent: March 14, 2017Assignee: Wistron NeWeb Corp.Inventors: Babak Radi, Yong-Jyun Lu, Ming-Chi Chiu, Chien-Min Hsu, Shih-Hong Chen
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Publication number: 20160192482Abstract: A method for forming a patterned conductive structure is provided. The method includes forming a soluble layer on a surface of a substrate, wherein the soluble layer has an opening exposing a rough portion of the surface. A first conductive layer is formed on the soluble layer, wherein the first conductive layer extends onto the rough portion in the opening. The soluble layer and the first conductive layer on the soluble layer are removed, wherein a portion of the first conductive layer corresponding to the rough portion is remained on the substrate. A patterned conductive structure formed by the method is also provided.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Babak RADI, Yong-Jyun LU, Ming-Chi CHIU, Chien-Min HSU, Shih-Hong CHEN
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Publication number: 20160174360Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.Type: ApplicationFiled: November 24, 2015Publication date: June 16, 2016Inventors: Chien-Min HSU, Shih-Hsien WU, Jing-Yao CHANG, Tao-Chih CHANG, Ren-Shin CHENG, Min-Lin LEE
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Patent number: 9030808Abstract: A capacitor and a circuit board having the same are provided. The capacitor includes a substrate, an oxide layer, a second electrode, an insulating layer, a plurality of conductive sheets and a plurality of vias. The substrate includes a first electrode and a porous structure. The porous structure in at least of two distribution regions has different depths. An oxide layer is disposed on the surface of the porous structure. The second electrode is disposed on the oxide layer and includes a conductive polymer material. The insulating layer disposed on the second electrode has a third and a fourth surfaces. The fourth surface of the insulating layer is connected with the second electrode. The conductive sheets are disposed on the first surface of the first electrode and the third surface of the insulating layer and electrically connected with the corresponding vias according to different polarities.Type: GrantFiled: September 10, 2012Date of Patent: May 12, 2015Assignee: Industrial Technology Research InstituteInventors: Chien-Min Hsu, Min-Lin Lee, Li-Duan Tsai
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Patent number: 9013893Abstract: An embedded capacitor module includes an electrode lead-out portion and at least one solid electrolytic capacitor portion adjacently disposed with the electrode lead-out portion. The electrode lead-out portion comprises a first substrate, a second substrate, a first insulating material disposed between the first substrate and the second substrate, a first porous layer formed on at least one surface of the first substrate, and a first oxide layer disposed on the first porous layer. The solid electrolytic capacitor portion comprises the first substrate, the second substrate, the first porous layer, the first oxide layer, all of which are extended from the electrode lead-out portion, a first conductive polymer layer disposed on the first oxide layer, a first carbon layer disposed on the first conductive polymer layer, and a first conductive adhesive layer disposed on the first carbon layer.Type: GrantFiled: May 17, 2013Date of Patent: April 21, 2015Assignee: Industrial Technology Research InstituteInventors: Chien-Min Hsu, Min-Lin Lee, Cheng-Liang Cheng, Li-Duan Tsai
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Patent number: 8941015Abstract: An embedded capacitor substrate module includes a substrate, a metal substrate and a solid electrolytic capacitor material. The solid electrolytic capacitor material is formed on the metal substrate, so as to form a solid electrolytic capacitor with the substrate. The embedded capacitor substrate module further includes an electrode lead-out region formed by extending the substrate and the metal substrate. The metal substrate serves as a first electrode, and the substrate serves as a second electrode. An insulating material is formed between the substrate and the metal substrate. Therefore, the embedded capacitor substrate module is not only advantageous in having a large capacitance as the conventional solid capacitor, but also capable of being drilled or plated and electrically connected to other circuits after being embedded in a printed circuit board.Type: GrantFiled: August 3, 2011Date of Patent: January 27, 2015Assignee: Industrial Technology Research InstituteInventors: Chien-Min Hsu, Min-Lin Lee, Cheng-Liang Cheng, Li-Duan Tsai