Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method is disclosed for sealing the edge of a wafer against slurry debris and contaminants that are encountered during grinding and backlapping of a semiconductor substrate. This is accomplished by depositing a photosensitive polyimide as a dielectric material on a wafer and mounting the wafer on a chuck. A light source is introduced above the wafer and close to the edge of the wafer. The chuck is then spun by means of a spindle, thus exposing an outer ring of the circumferential edge of the wafer to light source. Because polyimide behaves like a negative resist in the art of lithography, the exposed ring is fixed in place such that when the wafer is next developed, only the unexposed polyimide corresponding to the scribe line patterns is dissolved forming “scribe channels”, while leaving the ring in tact all along the circumference of the wafer.

Abstract: A method is disclosed for sealing the edge of a wafer against slurry debris and contaminants that are encountered during grinding and backlapping of a semiconductor substrate. This is accomplished by depositing a photosensitive polyimide as a dielectric material on a wafer and mounting the wafer on a chuck. A light source is introduced above the wafer and close to the edge of the wafer. The chuck is then spun by means of a spindle, thus exposing an outer ring of the circumferential edge of the wafer to light source. Because polyimide behaves like a negative resist in the art of lithography, the exposed ring is fixed in place such that when the wafer is next developed, only the unexposed polyimide corresponding to the scribe line patterns is dissolved forming "scribe channels", while leaving the ring in tact all along the circumference of the wafer.